Method for forming flowable dielectric layer in semiconductor device

• US 20050020093A1
• Filed: 12/19/2003
• Published: 01/27/2005
• Est. Priority Date: 07/24/2003
• Status: Active Grant

• Current Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Original Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Inventors: Ahn, Sang-Tae, Sheen, Dong-Sun, Song, Seok-Pyo
• Granted Patent: US 7,087,515 B2
• Time in Patent Office: Days
• US Class Current: 438/782
• CPC Class Codes: H01L 21/02063 the processing being the formation of vias or contact holes
• CPC Class Codes: H01L 21/76814 post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
• CPC Class Codes: H01L 21/7682 the dielectric comprising air gaps
• CPC Class Codes: H01L 21/76822 Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
• CPC Class Codes: H01L 21/76831 in via holes or trenches, e.g. non-conductive sidewall liners
• CPC Class Codes: H01L 2221/1047 the air gaps being formed by pores in the dielectric

Abstract

The method for forming a flowable dielectric layer is employed to use a barrier layer on sidewalls of patterned flowable dielectrics, thereby preventing a bridge phenomenon between adjacent contact plugs. The method includes steps of: forming a plurality of patterns on a semiconductor substrate, wherein narrow and deep gaps are formed therebetween; forming a flowable dielectric layer so as to fill the gaps between the patterns; carrying out an annealing process for densifying the flowable dielectric layer and removing moisture therein; forming a plurality of contact holes by selectively etching the flowable dielectric layer so as to expose predetermined portions of the semiconductor substrate; forming a barrier layer on sidewalls of the contact holes for preventing micro-pores in the flowable dielectric layer; carrying out a cleaning process in order to remove native oxides and defects on the semiconductor substrate; and forming a plurality of contact plugs by filling a conductive material into the contact plugs.

Claims

1. A method for forming a flowable dielectric layer in a semiconductor device, the method comprising the steps of:

a) forming a plurality of patterns on a semiconductor substrate, wherein narrow and deep gaps are formed therebetween;

b) forming a flowable dielectric layer so as to fill the gaps between the patterns;

c) carrying out an annealing process for densifying the flowable dielectric layer and removing moisture therein;

d) forming a plurality of contact holes by selectively etching the flowable dielectric layer so as to expose predetermined portions of the semiconductor substrate;

e) forming a barrier layer on sidewalls of the contact holes for preventing micro-pores in the flowable dielectric layer;

f) carrying out a cleaning process in order to remove native oxides and defects on the semiconductor substrate; and

g) forming a plurality of contact plugs by filling a conductive material into the contact plugs.

2. The method as recited in claim 1, wherein the step e) includes the steps of:

e1) forming an insulating layer over the resultant structure; and

e2) carrying out a dry etching so as to form spacers on the sidewalls of the contact holes.

3. The method as recited in claim 2, wherein the step e2) is carried out by using a blanket etch process.

4. The method as recited in claim 1, wherein the barrier layer employs a material selected from the group consisting of a silicon oxide, a silicon nitride and a silicon carbide.

5. The method as recited in claim 1, wherein the barrier layer is formed with a thickness in a range of about 20 _ to about 300 _.

6. The method as recited in claim 1, after the step d), further comprising the step of carrying out a pre-cleaning process for removing native oxides and the other impurities.

7. The method as recited in claim 1, wherein the step c) is carried out in a furnace at a temperature in a range of about 300 _ to about 1,000 _.

8. The method as recited in claim 1, wherein the step b) is carried out by using a spin on dielectric (SOD) selected from the group consisting of a silicate, a siloxane, a methyl SilsesQuioxane (MSQ), a hydrogen SisesQuioxane (HSQ), an MSQ/HSQ, a perhydrosilazane (TCPS) or a polysilazane.

9. The method as recited in claim 1, wherein the step b) is carried out by using a low temperature undoped dielectric at a temperature in a range of about −

10 _ to about 150 _ under a pressure ranging from about 10 mTorr to about 100 Torr, wherein a reaction source uses a mixture gas of SiH_x(CH₃)_y (0≦

x≦

4, 0≦

y≦

4), H₂O₂, O₂, H₂O and N₂O.