Dynamically adaptable semiconductor parametric testing

• US 20050021273A1
• Filed: 08/24/2004
• Published: 01/27/2005
• Est. Priority Date: 04/25/2002
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Blunn, Robert G., Velichko, Sergey A., Dorough, Michael J.
• Granted Patent: US 7,139,672 B2
• Time in Patent Office: Days
• US Class Current: 702/119
• CPC Class Codes: G01R 31/2831 Testing of materials or semi-finished products, e.g. semiconductor wafers or substrates G01R31/318511 takes precedence; testing during manufacture H01L22/00

Abstract

An apparatus, method, system, and signal-bearing medium may provide multiple maps, which may include multiple probing sequences to be called upon at run-time based on statistical thresholds or other selected criteria. Each map may include a series of locations on a wafer, the tests to perform at each location, and the measured results of each test. A parametric test system may perform the test at the associated location on the wafer. If the statistical threshold is exceeded or the selected criteria is met, the current map may be abandoned in favor of a different map.

Claims

1. A method of parametric testing of semiconductor wafers, comprising:

probing a subset of test locations on a wafer using a first map containing a first sequence of test locations on the wafer;

probing test locations using the first map while all of the subset of the test locations satisfy a first criteria specified in the first map; and

probing another subset of test locations on the wafer using a second map containing a second sequence of test locations on the wafer, when the first criteria exceeds a preselected failure threshold and before completion of the probing of the test locations using the first map.

2. The method of claim 1 wherein the first map is an intersection of a plurality of ordered map sets, wherein each of the map sets comprises at least one ordered site set, wherein each of the site sets comprises at least one ordered subsite set, and wherein each of the subsite sets comprises at least one ordered electrical measurement for each of the test locations.

3. The apparatus of claim 2, wherein the intersection defines one contiguous probe stepping sequence for the wafer to perform a series of electrical tests for defects.

4. The method of claim 3 further including controlling a parametric test control system to test the wafer using the intersection of the plurality of ordered map sets and wherein a statistical control limit of the parametric test control system causes a probe step sequence of the at least one ordered measurement to change the probe step sequence.

5. The method of claim 4 wherein the preselected failure threshold is a number of defects found at the test locations.

6. A method of parametric testing of semiconductor wafers, comprising:

preparing to electrically probe a sequence of first test locations on a wafer using a first map;

probing the first test locations using the first map as long as test results from the first test locations satisfy a defect threshold criteria specified by a user;

preparing to probe a sequence of second test locations using a second map;

switching from the first map to the second map when the test results from the first test locations do not satisfy the defect threshold criteria; and

probing the second test locations using the second map before completion of the probing of the first test locations.

7. The method of claim 6, wherein the switching further comprises determining a badsite count based on a number of bad test locations for the first map and a total number of sites on the first map and comparing the badsite count to the defect threshold test.

8. A method of parametric testing of semiconductor wafers, comprising:

instructing a prober to electrically probe a first set of test locations on a wafer based on a first probing sequence specified in a first map;

halting the prober prior to completion of the first probing sequence when a defect threshold is exceeded;

dynamically switching to a second probing sequence specified in a second map; and

probing a second test locations on the wafer based on the second probing sequence specified in the second map.

9. The method of claim 8, further comprising moving the prober in a user-defined pattern specified by the second map.

10. The method of claim 8, further comprising moving the prober in a serpentine pattern specified by the second map.

11. The method of claim 8, further comprising moving the prober in a row-by-row pattern specified by the second map.

12. A method of parametric testing of semiconductor wafers, comprising:

producing a plurality of maps each including a probing sequences for parametric testing of probe sites, each map including a series of locations on a wafer, a specific electrical test to perform at each location, and the expected and measured results of each test;

controlling a prober with a first of the plurality of maps, to move through the associated probing sequence and to perform the test at the associated location and record the results;

dynamically switching from the first of the maps to a second of the plurality of maps when combined results from each of the specific tests exceeds a failure threshold;

controlling the prober with the second of the plurality of maps, to move through the associated probing sequences and to perform the test at the associated location and record the results.

13. The method of claim 12, further comprising:

dynamically switching from the second of the maps to a third of the plurality of maps when combined results from each of the specific tests of the second map exceeds a failure threshold;

controlling the prober with the third of the plurality of maps, to move through the associated probing sequences and to perform the test at the associated location and record the results.

14. A method of parametric testing of semiconductor wafers, comprising:

probing a first set of test locations on a wafer based on a first probing sequence specified in a first map;

determining a failure count based on a number of defects found at test locations for the first map;

comparing the failure count to a total number of sites on the first map to determine a badsite count;

comparing a user-defined failure threshold to the badsite count; and

switching to a second probing sequence specified in a second map prior to completion of the first probing sequence when the badsite count exceeds the failure threshold.

15. The method of claim 14 further including halting the testing when the badsite count exceeds a preselected threshold.

17. The method of claim 15 further including updating the historical statistics with results from the first test locations.

16. A method of parametric testing of semiconductor wafers, comprising:

determining a defect threshold based upon historical statistics of testing a wafer lot;

instructing a prober to probe a plurality of first test locations on a wafer based on a first probing sequence specified in a first map;

switching to a second map having a second probing sequence prior to completion of the first probing sequence when the defect threshold is exceeded; and

halting the second probing sequence based on a badwafer threshold being exceeded.

18. The method of claim 16 further including updating the historical statistics with results from the second test locations.

19. The method of claim 16 further comprises determining the badwafer threshold based on a number of bad wafers for a lot run and a total number of wafers.

20. A method of parametric testing of semiconductor wafers, comprising:

loading a wafer for parametric testing;

forming a first intersection map from a first portion of a plurality of map sets which direct a first sequence of prober movements to perform parametric tests at each location in the first intersection map;

forming a second intersection map from a second portion of the plurality of map sets which direct a second sequence of prober movements to perform parametric tests at each location in the second intersection map;

forming a threshold parametric test value to switch from the first intersection map to the second intersection map when an error threshold is exceeded from the parametric tests;

instructing a prober to probe a plurality of first test locations on a wafer based on the first sequence of prober movements;

halting the prober prior to completion of the first sequence of prober movements when the error threshold is exceeded;

switching to the second intersection map having the second sequence of prober movements;

instructing the prober to probe a plurality of second test locations on the wafer based on the second sequence of prober movements; and

performing a parametric test at each location in the second intersection map.

21. The method of claim 20, wherein the first and second intersection maps define contiguous probe stepping sequences and testing procedures for the wafer.

22. The method of claim 20, wherein each of the plurality of map sets further comprises at least one ordered site set, wherein each of the site sets comprises at least one ordered subsite set, and wherein each of the subsite sets comprises at least one ordered measurement.

23. The method of claim 22, wherein the ordered measurement further comprises a key-value pair comprising a register key and an electrical test result value, and wherein the parametric test control system is to store a test measurement from the wafer in the electrical test result value.

24. A method of parametric testing of semiconductor wafers, comprising:

loading a wafer on a chuck;

aligning the wafer on the chuck;

calibrating a probe head to a location on the wafer;

reading a test plan for parametric testing of the wafer, the test plan including a first prober-movement map and a second prober-movement map;

probing the wafer based on the first prober-movement map of the test plan,

interrupting the probing of the wafer in response to an error threshold being exceeded;

selecting the second prober-movement map; and

probing the wafer based on the second prober-movement map.

25. The method of claim 24, further including determining the error threshold based upon historical test data from other wafers.

26. The method of claim 24, further including determining the error threshold based upon user input.

27. A method of parametric testing of semiconductor wafers, comprising:

loading a first semiconductor wafer onto a probing machine having a probe head;

loading a first map selected from a plurality of map sets, the first map operable for directing a first sequence of prober movements to perform parametric tests at each location in the first map;

loading a second map selected from the plurality of map sets, the second map operable for directing a second sequence of prober movements to perform parametric tests at each location in the first map;

loading a parametric test defect threshold determined from historical data of testing other wafers;

moving the probe head in the first sequence of prober movements specified in the first map;

probing test pins with the probe head to perform tests on the wafer at each location in the first probing sequence;

recording test results of each test at each respective location;

halting the prober when the test results indicate the defect threshold has been exceeded;

switching from the first map to the second map;

moving the probe head in the second sequence of prober movements specified in the second map; and

recording test results of each test at each respective location.

28. The method of claim 27, wherein the halting occurs prior to completion of the first probing sequence.

29. The method of claim 27, wherein halting includes removing electrical test stimuli from the wafer prior to the switching between the maps.

30. The method of claim 27, wherein switching includes switching from the first map being a composite wafer map to the second map being an aggregate wafer map.