SELF-CONTAINED PROCESSOR SUBSYSTEM AS COMPONENT FOR SYSTEM-ON-CHIP DESIGN

• US 20050021871A1
• Filed: 07/25/2003
• Published: 01/27/2005
• Est. Priority Date: 07/25/2003
• Status: Active Grant

• Current Assignee: Microsoft Technology Licensing LLC (Microsoft Corporation)
• Original Assignee: International Business Machines Corporation
• Inventors: Salapura, Valentina, Gregurick, Victor L., Georgiou, Christos J.
• Granted Patent: US 7,353,362 B2
• Time in Patent Office: Days
• US Class Current: 709/250
• CPC Class Codes: G06F 15/7832 on one IC chip (single chip microprocessors)
• CPC Class Codes: H04L 49/109 Integrated on microchip, e.g. switch-on-chip
• CPC Class Codes: H04L 49/602 Multilayer or multiprotocol switching, e.g. IP switching

Abstract

A System-on-Chip (SoC) component comprising a single independent multiprocessor subsystem core including a plurality of multiple processors, each multiple processor having a local memory associated therewith forming a processor cluster; and a switch fabric means connecting each processor cluster within an SoC integrated circuit (IC). The single SoC independent multiprocessor subsystem core is capable of performing multi-threading operation processing for SoC devices when configured as a DSP, coprocessor, Hybrid ASIC, or network processing arrangements. The switch fabric means additionally interconnects a SoC local system bus device with SoC processor components with the independent multiprocessor subsystem core.

Claims

1. A microprocessor subsystem for use in a system-on-chip (SoC) integrated circuit (IC) comprising a communications bus device, said microprocessor sub-system comprising:

two or more microprocessor devices formed as a single processor core assembly and capable of performing operations to implement a given processing functionality;

a memory storage device associated with said two or more microprocessor devices in said sub-system for storing at least one of data and instructions in said single processor core assembly;

an interconnect means residing in said single processor core assembly for enabling communication between said two or more microprocessor devices and said SoC IC communications bus device, whereby said single processor core assembly may communicate with components of said SoC IC.

2. The microprocessor subsystem as claimed in claim 1, wherein said two or more microprocessor devices of said single processor core assembly operate under program control to enable a specific set of functionalities.

3. The microprocessor subsystem as claimed in claim 1, wherein said interconnect means comprises a switch fabric.

4. The microprocessor subsystem as claimed in claim 1, wherein said interconnect means comprises a communications bus.

5. The microprocessor subsystem as claimed in claim 2, wherein said SoC IC is a network processor assembly, said microprocessor subsystem implementing packet communications processing functionality.

6. The microprocessor subsystem as claimed in claim 5, wherein said single processor core assembly further comprises one or more interface devices capable of receiving communications according to a network communications protocol including one or more from the group comprising:

Fibre Channel, Gb Ethernet, Infiniband.

7. The microprocessor subsystem as claimed in claim 6, wherein said network processor assembly is configured as one of a DSP, coprocessor, Hybrid ASIC, or other network processing arrangement, said network processing assembly comprising:

a network processing device, and

a high-speed local bus means for interconnecting components of said network processing assembly with said network processing device.

8. The microprocessor subsystem as claimed in claim 7, wherein components of said network processor assembly include one or more selected from the group comprising:

an SRAM, a DDR controller, a PCI-X bridge, a direct memory access DMA device, a DMA controller, an on-chip peripheral bus (OPB) for interfacing with external components via one or more I/O interface devices, and a Medium Access Control (MAC) protocol device employed to provide a data link layer interface to an Ethernet local area network (LAN) system.

9. The microprocessor subsystem as claimed in claim 1, wherein said single processor core assembly further comprises a programmable processor local bus bridge device for enabling data flow between the microprocessor subsystem and said communications bus device of said SoC IC.

10. The microprocessor subsystem as claimed in claim 9, wherein said programmable processor local bus bridge device adapts communications signals and signaling protocols between two communication systems communicating via said SoC IC device implementing said single processor core assembly.

11. The microprocessor subsystem as claimed in claim 1, wherein said interconnect means comprises a crossbar switch for tying together independent thread groups corresponding to two or more microprocessor devices.

12. The microprocessor subsystem as claimed in claim 1, wherein said local memory storage device associated with said two or more microprocessor devices in said sub-system includes one or more of:

a local SRAM memory, a memory cache, and an I-cache connecting the sub-processors together.

13. The microprocessor subsystem as claimed in claim 8, wherein said two or more microprocessor devices of said single processor core assembly comprises means for polling a communications bus device of said SoC IC for handling processing of one or more network protocol communications.

14. A system-on-chip (SoC) Integrated Circuit (IC) network processor architecture comprising:

a network processor core for controlling SoC network processor functions among a plurality of network processor components;

an SoC local system bus device for enabling communications among said SoC network processor components,

one SoC network processor component comprising an independent multiprocessor subsystem core comprising;

i) at least one microprocessor implementing a given functionality;

ii) at least one memory storage device for storing at least one of data and instructions; and

iii) interconnect means for enabling high speed communication between two or more microprocessor devices and said SoC IC local system bus device,

wherein said single SoC multiprocessor subsystem core provides multi-threading network processing capability.

15. The SoC IC network processor architecture as claimed in claim 14, wherein said single SoC multiprocessor sub-system core further comprises one or more interface devices capable of receiving communications according to a network communications protocol including one or more from the group comprising:

Fibre Channel, Gb Ethernet, Infiniband.

16. The SoC IC network processor architecture as claimed in claim 15, configured as one of a DSP, coprocessor, Hybrid ASIC, or other network processing arrangement, wherein said SoC local system bus device is a high-speed local bus means for interconnecting said SoC network processor components with said network processing core.

17. The SoC IC network processor architecture as claimed in claim 16, wherein said network processor components include one or more selected from the group comprising:

an SRAM, a DDR controller, a PCI-X bridge, a direct memory access DMA device, a DMA controller, an on-chip peripheral bus (OPB) for interfacing with external components via one or more I/O interface devices, and a Medium Access Control (MAC) protocol device employed to provide a data link layer interface to an Ethernet local area network (LAN) system.

18. The SoC IC network processor architecture as claimed in claim 14, wherein said multiprocessor subsystem core further comprises a programmable processor local bus bridge device for enabling data flow between the microprocessor subsystem and said SoC local system bus device.

19. The SoC IC network processor architecture as claimed in claim 18, wherein said programmable processor local bus bridge device adapts communications signals and signaling protocols between two communication systems communicating via said SoC IC device implementing said single multiprocessor subsystem core.

20. The SoC IC network processor architecture as claimed in claim 14, wherein said interconnect means of said single multiprocessor subsystem core comprises a crossbar switch for tying together independent thread groups corresponding to two or more microprocessor devices.

21. The SoC IC network processor architecture as claimed in claim 14, wherein said at least one memory storage device associated with said two or more microprocessor devices in said sub-system includes one or more of:

a local SRAM memory, a memory cache, and an I-cache for connecting the microprocessor devices together.

22. The SoC IC network processor architecture as claimed in claim 21, wherein said single multiprocessor subsystem core comprises means for polling a local system bus device of said SoC IC for handling processing of one or more network protocol communications.

23. A system-on-chip (SoC) processor Integrated Circuit (IC) architecture comprising:

a processor core for controlling SoC processing functions among a plurality of SoC component devices;

an SoC local system bus device for enabling communications among said SoC component devices, one SoC component device comprising a single independent multiprocessor subsystem core comprising;

a plurality of multiple processors, each multiple processor having a local memory associated therewith forming a processor cluster; and

a switch fabric means connecting each processor cluster within said SoC IC,

wherein said single SoC multiprocessor subsystem core is capable of performing multi-threading operation processing.

24. The system-on-chip (SoC) processor Integrated Circuit (IC) architecture as claimed in claim 23, wherein said independent multiprocessor subsystem core comprising a plurality of multiple processors implements predefined set of functionality for use as a functional SoC component, said switch fabric connecting each processor cluster within said SoC IC enabling data traffic flow for processing required by said functionality within said core.

25. The system-on-chip (SoC) processor Integrated Circuit (IC) architecture as claimed in claim 23, wherein said switch fabric means further enables communication of data traffic and instruction traffic for processing required by said functionality within said core.

26. The system-on-chip (SoC) processor Integrated Circuit (IC) architecture as claimed in claim 23, wherein said switch fabric means comprises a crossbar switch that organizes independent thread groups within the multiprocessor subsystem core in a cellular fashion.

27. The system-on-chip (SoC) processor Integrated Circuit (IC) architecture as claimed in claim 26, wherein each of said plurality of multiple processors includes a local SRAM memory, one of an arithmetic logic unit (ALU) or floating point unit (FPU) and corresponding data cache, and, an instruction cache (I-cache) foe connecting processor thread groups together.

28. The system-on-chip (SoC) processor Integrated Circuit (IC) architecture as claimed in claim 26, wherein said single independent multiprocessor subsystem core functions in an SoC implementation including one of:

a microprocessor, DSP, coprocessor, Hybrid ASIC″

s, or another network processor arrangement.

29. The system-on-chip (SoC) processor Integrated Circuit (IC) architecture as claimed in claim 26, wherein the associated local memory memory of the processor cluster includes a local SRAM, or on-chip DRAM.

30. The system-on-chip (SoC) processor Integrated Circuit (IC) architecture as claimed in claim 26, further including a software polling connection means to direct bus and I/O media connections, said polling connection means polling said SoC local system bus device to handle one or more network protocols.