Determining target operating frequencies for a multiprocessor system

• US 20050022038A1
• Filed: 07/23/2003
• Published: 01/27/2005
• Est. Priority Date: 07/23/2003
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Kaushik, Shivnandan D., Sager, Ping
• Granted Patent: US 7,146,514 B2
• Time in Patent Office: Days
• US Class Current: 713/300
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/324 by lowering clock frequency
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

In one embodiment of the present invention, a method includes determining utilization values for a plurality of processors having power utilization dependencies, and identifying a target frequency for the plurality of processors based on the utilization values.

Claims

1. A method comprising:

determining utilization values for a plurality of processors having power utilization dependencies; and

identifying a target frequency for the plurality of processors based on the utilization values.

2. The method of claim 1, further comprising transitioning a processor package to the target frequency, the processor package including the plurality of processors.

3. The method of claim 1, further comprising obtaining parameter information for the plurality of processors.

4. The method of claim 3, further comprising determining the utilization values using the parameter information.

5. The method of claim 1, wherein the utilization values comprise an up/down decision for each of the plurality of processors.

6. The method of claim 2, wherein identifying the target frequency comprises identifying a frequency operating point closest to a maximum operating frequency of the processor package multiplied by a maximum utilization of one of the plurality of processors having a highest value for the maximum utilization.

7. The method of claim 2, further comprising transitioning the processor package to a higher frequency if one of the utilization values is an up decision.

8. The method of claim 2, further comprising transitioning the processor package to a lower frequency if all of the utilization values are a down decision.

9. The method of claim 1, wherein the plurality of processors comprise a plurality of logical processors.

10. The method of claim 1, wherein the plurality of processors comprise at least one multicore processor.

11. A method comprising:

determining utilization decisions for logical processors of a physical processor using parameter information; and

calculating a target frequency for the physical processor based on the utilization decisions.

12. The method of claim 11, further comprising transitioning the physical processor to the target frequency.

13. The method of claim 11, further comprising transitioning the physical processor to a higher frequency if any of the logical processors has an up utilization decision.

14. The method of claim 13, wherein the higher frequency is based on a highest utilization processor of the logical processors.

15. The method of claim 11, further comprising transitioning the physical processor to a lower frequency if all of the logical processors have a down utilization decision.

16. The method of claim 15, wherein the lower frequency is based on a highest utilization processor of the logical processors.

17. The method of claim 12, wherein transitioning the physical processor comprises transitioning to a higher frequency if any of the logical processors needs additional compute power.

18. The method of claim 11, wherein calculating the target frequency is based on desired power and performance characteristics.

19. An article comprising a machine-readable storage medium containing instructions that if executed enable a system to:

determine utilization values for a plurality of processors having power utilization dependencies; and

identify a target frequency for the plurality of processors based on the utilization values.

20. The article of claim 19, further comprising instructions that if executed enable the system to transition a processor package to the target frequency, the processor package including the plurality of processors.

21. The article of claim 20, further comprising instructions that if executed enable the system to identify a frequency operating point closest to a maximum operating frequency of the processor package multiplied by a maximum utilization of one of the plurality of processors having a highest value for the maximum utilization.

22. The article of claim 20, further comprising instructions that if executed enable the system to transition the processor package to a higher frequency if any of the plurality of processors needs additional compute power.

23. The article of claim 20, further comprising instructions that if executed enable the system to transition the processor package to a lower frequency if any of the plurality of processors needs less power.

24. A system comprising:

a plurality of processors; and

a dynamic random access memory containing instructions that if executed enable the system to determine utilization values for the plurality of processors and to identify a target frequency for the plurality of processors based on the utilization values.

25. The system of claim 24, wherein the plurality of processors comprises a plurality of logical processors within a processor package.

26. The system of claim 25, further comprising instructions that if executed enable the system to identify a frequency operating point closest to a maximum operating frequency of the processor package multiplied by a maximum utilization of one of the plurality of logical processors having a highest value for the maximum utilization.

27. The system of claim 25, further comprising instructions that if executed enable the system to transition the logical processor package to a higher frequency if any of the plurality of logical processors needs additional compute power.