Apparatus and method for memory with bit swapping on the fly and testing

• US 20050022065A1
• Filed: 05/19/2004
• Published: 01/27/2005
• Est. Priority Date: 05/20/2003
• Status: Active Grant

• Current Assignee: CRAY Incorporated (Hewlett-Packard Enterprise Company)
• Original Assignee: CRAY Incorporated (Hewlett-Packard Enterprise Company)
• Inventors: Resnick, David R., Bethard, Roger A., Snyder, Van L., Higgins, Michael F., Schwoerer, Gerald A., Grossmeier, Alan M., Marquardt, Kelly J., Steinberger, Michael L., Dixon, R. Paul
• Granted Patent: US 7,320,100 B2
• Time in Patent Office: Days
• US Class Current: 714/42
• CPC Class Codes: G06F 11/106 Correcting systematically all correctable errors, i.e. scrubbing
• CPC Class Codes: G11C 11/401 forming cells needing refreshing or charge regeneration, i.e. dynamic cells
• CPC Class Codes: G11C 2029/0401 in embedded memories
• CPC Class Codes: G11C 29/44 Indication or identification of errors, e.g. for repair
• CPC Class Codes: G11C 29/4401 for self repair
• CPC Class Codes: G11C 29/848 by adjacent switching

Abstract

A memory controller and method that provide a read-refresh (also called “distributed-refresh”) mode of operation, in which every row of memory is read within the refresh-rate requirements of the memory parts, with data from different columns within the rows being read on subsequent read-refresh cycles until all rows for each and every column address have been read, scrubbing errors if found, thus providing a scrubbing function that is integrated into the read-refresh operation, rather than being an independent operation. For scrubbing, an atomic read-correct-write operation is scheduled. A variable-priority, variable-timing refresh interval is described. An integrated card self-tester and/or card reciprocal-tester is described. A memory bit-swapping-within-address-range circuit, and a method and apparatus for bit swapping on the fly and testing are described.

Claims

1. An information-processing apparatus comprising:

a first memory having a plurality of addressed locations, each location holding a plurality of bits; and

a first control circuit, the control circuit including;

a first memory controller, the memory controller including;

an address-range detector that specifies a range spanning a subset of the addressed locations, and that, for each memory request, determines whether an address of the memory request is within the specified range; and

a read-data bit-swap circuit coupled to receive data from the first memory and operatively coupled to the address-range detector, and based on an indication from the address-range detector as to whether a memory request address is within the range, to swap one or more bits of the data.

2. The apparatus of claim 1, the first control circuit further including:

a test engine operatively coupled to the first memory controller and configured to provide test functions to verify whether, for memory requests having addresses within the range, the one or more bits are swapped,

wherein the first control circuit is located on a first memory card, and the test engine is located on a second memory card that is substantially identical to the first memory card.

3. The apparatus of claim 1, the first memory controller further comprising:

a write-data bit-swap circuit coupled to transmit data to the memory and operatively coupled to the address-range detector, and based on an indication from the address-range detector as to whether a memory request address is within the range, to swap one or more bits of the data.

4. The apparatus of claim 3, the first control circuit further including:

a test engine operatively coupled to the first memory controller and configured to provide testing functions to verify whether, for memory requests having addresses within the range, the one or more bits are swapped, and for memory requests having addresses outside the range, the one or more bits are not swapped.

5. The apparatus of claim 1, the first memory controller further comprising:

an address changer operatively coupled to the address-range detector to adjust an end of the specified range.

6. The apparatus of claim 1, the first memory controller further comprising:

a section-swap controller operatively coupled to initialize the address range detector and address incrementer, and to control, for each location within a set of memory locations of memory, a section-swap operation that uses an atomic read-write operation that reads data from the location in memory using a first bit-mapping configuration and to writes data back to the location in memory using a second bit-mapping configuration different than the first.

7. The apparatus of claim 6, the first control circuit further including:

a test engine operatively coupled to the first memory controller and configured to provide testing functions to verify whether, the section-swap controller properly functions to control the atomic reading and writing such that normal read operations and write operations obtain correct data during the section-swap operation.

8. The apparatus of claim 6, the first memory controller further comprising:

an error-correction circuit that, for at least some of the atomic read-write operations, corrects an error in the read data and generates corrected data for the write.

9. The apparatus of claim 8, the first memory controller further comprising:

a processor memory-request controller that, interleaved between the atomic read-write operations, performs processor memory operations both within the specified range and outside of the specified range.

10. The apparatus of claim 9, further comprising:

a memory-request buffer configured to hold a plurality of pending memory requests, wherein the error-correction circuit corrects errors based on a SECDED ECC, and wherein, for each atomic read-write operation, the section-swap controller operates to inhibit further operations from issuing from the memory-request buffer and allowing already issued and pending memory requests to complete and, at least to the extent needed to prevent conflicting accesses, preventing further memory requests from being issued for a period of time to allow the atomic read-write operation to effectively complete.

11. The apparatus of claim 9, further comprising:

a memory-request buffer configured to hold a plurality of pending memory requests, wherein the error-correction circuit corrects errors based on a ECC, and wherein, for each atomic read-write operation, the section-swap controller operates to inhibit further operations from issuing from the memory-request buffer and allowing already issued and pending memory requests to complete and preventing further memory requests from being issued for a period of time to allow the atomic read-write operation to effectively complete.

12. The apparatus of claim 8, further comprising

a refresh controller, coupled to the memory-request buffer, and configured to send read-refresh requests using refresh addresses that cycle through address bits for a first-address portion of the refresh address and also cycle through bits for a second-address portion of the refresh address, and wherein read-refresh data is fetched to the memory interface and checked by an error detector as a result of each of the read-refresh requests.

13. The apparatus of claim 8, wherein the refresh controller is configured to use the read-refresh data that was read for a read-refresh operation as the source data for a swap-and-write portion of an atomic read-swap-write operation.

14. The apparatus of claim 12, wherein the first address portion includes address bits for a row of data in a memory chip and the second address portion includes address bits for a column of data in the memory chip.

15. The apparatus of claim 12, wherein the refresh controller is further configured to send explicit-refresh requests to the memory-request buffer, wherein the explicit-refresh requests are sent to the memory to cause the memory to perform an internally controlled refresh function.

16. The apparatus of claim 15, wherein the refresh controller further includes a timer controller that allows the timing between explicit-refresh requests to be varied.

17. The apparatus of claim 12, wherein the refresh controller further includes a priority controller that sends a first read-refresh request at an initial priority value, and later if the first read-refresh request has not been completed, increases the priority value.

18. The apparatus of claim 12, wherein the refresh controller further includes a priority controller that sends a first read-refresh request specifying a first address and at an initial priority value, and later if the first read-refresh request has not been completed, then sends a second read-refresh request specifying the first address and at a higher priority value to replace the first read-refresh request.

19. The apparatus of claim 1, further comprising:

a plurality of high-speed serial external interfaces;

a second memory controller substantially the same as the first memory controller;

a second memory operatively coupled to the second memory controller; and

a crossbar switch operatively coupled to transmit and receive memory commands and data to and from the first and second memory controllers, and to and from the plurality of high-speed serial external interfaces.

20. The apparatus of claim 18, wherein the apparatus is packaged on a single first memory card.

21. The apparatus of claim 20, further comprising:

a second memory card substantially the same as the first memory card;

a first plurality of processors coupled to the first memory card and to the second memory card;

a third and fourth memory card each substantially the same as the first memory card;

a second plurality of processors coupled to the third memory card and to the fourth memory card;

a network operatively coupled between the first plurality of processors and the second plurality of processors; and

an input/output system operatively coupled to provide data to and from the first plurality of processors.

22. The apparatus of claim 20, further comprising:

a first plurality of processors coupled to the plurality of high-speed serial external interfaces;

a network operatively coupled to each of the first plurality of processors;

an input/output system operatively coupled to provide data to and from the first plurality of processors; and

a power supply operatively coupled to provide power to the first plurality of processors.

23. An information-processing method comprising:

receiving a first memory request;

detecting whether an address of the first memory request is within a specified range of addresses;

swapping a subset of bit positions of a first of data based on the first address being detected as within the specified range; and

writing the bit-swapped first data to the memory.

24. The method of claim 23, further comprising:

receiving a second memory request;

detecting whether an address of the second memory request is within a specified set of addresses;

fetching second data based on a second memory request address; and

not swapping bits of the second data based on the second address being detected as not within the specified set.

25. The method of claim 24, wherein the receiving of the second memory request occurs just prior in time to the first memory request, and wherein the detecting of whether an address is within a specified set of addresses is performed on each one of a plurality of sequential accesses.

26. The method of claim 24, further comprising:

changing an end address of the specified set between the second and first memory requests, wherein the second address equals the first address such that data based on the read second data is bit-swapped to produce the first data and written to its same address.

27. The method of claim 26, further comprising:

performing error correction on the read data before bit swapping and writing.

28. The method of claim 27, further comprising:

iteratively changing the end address and reading and writing data in a section of the memory in order to dynamically move data in the section of the memory from a normal bit mapping configuration to a bit-swapped mapping configuration.

29. The method of claim 26, further comprising:

buffering a first plurality of pending memory requests from a processor;

sending a stream of the first processor memory requests from the buffered pending memory requests to the memory; and

stopping servicing of processor memory requests in order to perform fetching the second data and writing the first data atomically.

30. The method of claim 29, further comprising:

inserting a read-refresh request periodically into the stream of processor memory requests, wherein the periodic read-refresh requests are sent using refresh addresses that cycle through address bits for a row-address portion and also cycle through bits for a column-address portion;

fetching data as a result of each of the read-refresh requests;

detecting an error in one of the fetched sets of data; and

based on one or more criteria that include the detecting of the error, performing the bit-swapping operations.

31. The method of claim 30, further comprising varying a value of time between read-refresh requests.

32. The method of claim 30, further comprising varying a priority of the read-refresh requests.

33. The method of claim 30, further comprising inserting an explicit-refresh request periodically into the stream of memory requests to cause memory parts to perform an internally controlled refresh function.

34. The method of claim 30, wherein the method is performed on a single memory card.

35. An information-processing system comprising:

a memory;

address checking means for checking the address of each one of a plurality of memory requests from a processor that are transmitted to the memory; and

means for changing a mapping of bits that are read from and written to the memory.

36. The system of claim 35, further comprising means for testing the mapping of bits.

37. The system of claim 35, further comprising:

means for read-refreshing the memory and fetching read-refresh data as a result and correcting errors if errors are detected.

38. The system of claim 37, further comprising means for varying timing between read-refresh requests.

39. The system of claim 37, further comprising means for varying a priority of read-refresh requests.

40. The system of claim 35, further comprising means for explicitly refreshing the memory.

41. The system of claim 37, further comprising means for explicitly refreshing the memory in a manner periodically alternated with the read-refreshing of the memory.

42. The system of claim 40, further comprising:

means for varying timing between explicit requests.

43. The system of claim 42, further comprising:

means for varying a priority of explicit requests.

44. A computer-readable medium having control data thereon for causing a suitably programmed information-processing system to execute a method comprising:

receiving a first memory request;

detecting whether an address of the first memory request is within a specified set of addresses;

swapping a subset of bit positions of a first of data based on the first address being detected as within the specified set; and

writing the bit-swapped first data to the memory.

45. The medium of claim 44, wherein the method further comprises:

receiving a second memory request;

detecting whether an address of the second memory request is within a specified set of addresses;

fetching second data based on a second memory request address; and

not swapping bits of the second data based on the second address being detected as not within the specified set.