Error-detection cell for an integrated processor

• US 20050022071A1
• Filed: 07/08/2004
• Published: 01/27/2005
• Est. Priority Date: 07/09/2003
• Status: Active Grant

• Current Assignee: Stmicroelectronics France (STMicroelectronics NV)
• Original Assignee: STMicroelectronics SA (STMicroelectronics NV)
• Inventors: Teglia, Yannick, Liardet, Pierre-Yvan
• Granted Patent: US 7,363,547 B2
• Time in Patent Office: Days
• US Class Current: 714/48
• CPC Class Codes: G06F 11/0721 within a central processing unit [CPU]
• CPC Class Codes: G06F 11/0751 Error or fault detection not based on redundancy power supply failures G06F1/30; network fault management H04L41/06
• CPC Class Codes: G06F 21/52 during program execution, e.g. stack integrity ; Preventing unwanted data erasure; Buffer overflow
• CPC Class Codes: G06F 21/71 to assure secure computing or processing of information

Abstract

A cell for detecting a disturbance capable of affecting the operation of a processor in which it is integrated, including circuitry for holding an invariant in normal operation of the processor and for detecting an invariant loss consecutive to the occurrence of a disturbance.

Claims

1. An integrated cell for detecting a disturbance capable of affecting the operation of a processor, comprising:

non-volatile storage means for storing at least one value of the verification of an invariant; and

means for periodically recalculating said value in volatile memory elements, for holding an invariant in normal operation of the processor and for detecting an invariant loss consecutive to the occurrence of a disturbance.

2. The cell of claim 1, wherein the disturbance acts through the power supply of the cell and of the processor.

3. The cell of claim 1, wherein the cell comprises means for checking the invariant by comparing said value stored in the non-volatile memory element with a periodically-calculated current value.

4. The cell of claim 1, comprising two first registers intended to contain two preloaded data having a sum equal to said value stored in the non-volatile memory element, and a third register intended to contain the result of the sum of the first two, periodically calculated to be compared to the value stored in the non-volatile memory element, to check the invariant.

5. The cell of claim 4, wherein the data are preloaded into the first and second registers at each beginning of the execution of a program to be monitored.

6. An integrated processor, comprising at least one detection cell of claim 1.