Error-detection cell for an integrated processor
First Claim
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1. An integrated cell for detecting a disturbance capable of affecting the operation of a processor, comprising:
- non-volatile storage means for storing at least one value of the verification of an invariant; and
means for periodically recalculating said value in volatile memory elements, for holding an invariant in normal operation of the processor and for detecting an invariant loss consecutive to the occurrence of a disturbance.
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Abstract
A cell for detecting a disturbance capable of affecting the operation of a processor in which it is integrated, including circuitry for holding an invariant in normal operation of the processor and for detecting an invariant loss consecutive to the occurrence of a disturbance.
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Citations
6 Claims
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1. An integrated cell for detecting a disturbance capable of affecting the operation of a processor, comprising:
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non-volatile storage means for storing at least one value of the verification of an invariant; and
means for periodically recalculating said value in volatile memory elements, for holding an invariant in normal operation of the processor and for detecting an invariant loss consecutive to the occurrence of a disturbance. - View Dependent Claims (2, 3, 4, 5, 6)
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Specification