Vertical charge control semiconductor device with low output capacitance

• US 20050023607A1
• Filed: 08/31/2004
• Published: 02/03/2005
• Est. Priority Date: 07/18/2002
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Peter H. Wilson, Steven Sapp
• Inventors: Wilson, Peter H., Sapp, Steven
• Granted Patent: US 7,291,894 B2
• Time in Patent Office: Days
• US Class Current: 257/329
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/405 Resistive arrangements, e.g. resistive or semi-insulating field plates
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

In accordance with an embodiment of the present invention, a MOSFET includes at least two insulation-filled trench regions laterally spaced in a first semiconductor region to form a drift region therebetween, and at least one resistive element located along an outer periphery of each of the two insulation-filled trench regions. A ratio of a width of each of the insulation-filled trench regions to a width of the drift region is adjusted so that an output capacitance of the MOSFET is minimized.

Claims

1. A MOSFET comprising:

at least two insulation-filled trench regions laterally spaced in a first semiconductor region to form a drift region therebetween; and

at least one resistive element located along an outer periphery of each of the two insulation-filled trench regions,

wherein a ratio of a width of each of the insulation-filled trench regions to a width of the drift region is adjusted so that an output capacitance of the MOSFET is minimized.

2. A MOSFET comprising:

a first semiconductor region having a first surface; and

first and second insulation-filled trench regions each extending from the first surface into the first semiconductor region, each of the first and second insulation-filled trench regions having an outer layer of silicon of a conductivity type opposite that of the first semiconductor region,

wherein the first and second insulation-filled trench regions are spaced apart in the first semiconductor region to form a drift region therebetween, the volume of each of the first and second trench regions being greater than one-quarter of the volume of the drift region.

3. The MOSFET of claim 2 wherein the outer layer of silicon is a lightly doped silicon so that a depletion region formed in the first semiconductor region during an operation mode of the MOSFET is extended into the first semiconductor region away from the first surface.

4. The MOSFET of claim 2 further comprising:

a body region extending from the first surface into the first semiconductor region, the body region being of a conductivity type opposite that of the first semiconductor region;

a source region in the body region, the source region being of the same conductivity type as the first semiconductor region;

a second trench region extending from the first surface into the first semiconductor region; and

a gate in the second trench region extending across a portion of the body region and overlapping the source and the first semiconductor regions such that a channel region extending perpendicularly to the first surface is formed in the body region between the source and first semiconductor regions.

5. The MOSFET of claim 2 further comprising:

first and second body regions each extending from the first surface into the first semiconductor region, the first body region being laterally spaced from the second body region to form a JFET region therebetween, the first and second body regions being of a conductivity type opposite that of the first semiconductor region; and

first and second source regions in the first and second body regions respectively, the first and second source regions being of the same conductivity type as the first semiconductor region.

6. The MOSFET of claim 5 further comprising a gate extending over but being insulated from the JFET region and a portion of the first and second body regions, and overlapping the first and second source regions such that a channel region is formed along a body surface of each of the first and second body regions between the corresponding source and JFET regions.

7. The MOSFET of claim 5 further comprising:

a gate extending over but being insulated from each of the first and second body regions such that a channel region is formed along a surface of each of the first and second body regions between the corresponding source and JFET regions, the gate being discontinuous over a surface of the JFET region between the first and second body regions.

8. A MOSFET comprising:

a first semiconductor region over a substrate, the first semiconductor region having a first surface; and

first and second insulation-filled trench regions each extending from the first surface to a predetermined depth within the first semiconductor region, each of the first and second insulation-filled trench regions having an outer layer of doped silicon material which is discontinuous along a bottom surface of the insulation-filled trench region so that the insulation material along the bottom surface of the insulation-filled trench region is in direct contact with the first semiconductor region, the outer layer of silicon material being of a conductivity type opposite that of the first semiconductor region.

9. The MOSFET of claim 8 wherein the first and second insulation-filled trench regions are spaced apart in the first semiconductor region to form a drift region therebetween, the volume of each of the first and second insulation-filled trench regions being greater than one-quarter of the volume of the drift region.

10. The MOSFET of claim 8 wherein the outer layer of doped silicon of each of the first and second insulation-filled trench regions is lightly doped so that a depletion region formed in the first semiconductor region during an operation mode of the MOSFET is further extended into the first semiconductor region away from the first surface.

11. The MOSFET of claim 8 further comprising:

a body region extending from the first surface into the first semiconductor region, the body region being of a conductivity type opposite that of the first semiconductor region;

a source region in the body region, the source region being of the same conductivity type as the first semiconductor region;

a second trench region extending from the first surface into the first semiconductor region; and

a gate in the second trench region extending across a portion of the body region and overlapping the source and the first semiconductor regions such that a channel region extending perpendicularly to the first surface is formed in the body region between the source and first semiconductor regions.

12. The MOSFET of claim 8 further comprising:

first and second body regions each extending from the first surface into the first semiconductor region, the first body region being laterally spaced from the second body region to form a JFET region therebetween, the first and second and body regions being of a conductivity type opposite that of the first semiconductor region; and

first and second source regions in the first and second body regions respectively, the first and second source regions being of the same conductivity type as the first semiconductor region.

13. The MOSFET of claim 12 further comprising a gate extending over but being insulated from the JFET region and a portion of the first and second body regions, and overlapping the first and second source regions such that a channel region is formed along a body surface of each of the first and second body regions between the corresponding source and JFET regions.

14. The MOSFET of claim 12 further comprising:

a gate extending over but being insulated from each of the first and second body regions such that a channel region is formed along a surface of each of the first and second body regions between the corresponding source and JFET regions, the gate being discontinuous over a surface of the JFET region between the first and second body regions.

15. The MOSFET of claim 8 further comprising a termination structure, the termination structure comprising:

a termination trench region extending from the first surface into the first semiconductor region, the termination trench being filled with a semi-insulating material, the semi-insulating material being insulated from the first semiconductor region.

16. The MOSFET of claim 15 wherein the termination trench region is laterally spaced from the first and second trench regions so that during an operating mode of the MOSFET a substantially uniform electric field in the region between the termination trench region and the first and second trench regions is obtained.

17. The MOSFET of claim 15 wherein the semi-insulating material extends over the first surface in a direction away from the first and second trench regions such that during an operating mode of the MOSFET the electric field in the first semiconductor region under the portion of the semi-insulating material extending over the first surface is substantially reduced.

18. The MOSFET of claim 8 further comprising a termination structure, the termination structure comprising:

an insulation-filled termination trench region extending from the first surface into the first semiconductor region, the termination trench region being laterally spaced from the first and second trench regions so that during an operating mode of the MOSFET a substantially uniform electric field in the region between the termination trench region and the first and second trench regions is obtained.