Atomic layer-deposited HfAlO3 films for gate dielectrics

• US 20050023624A1
• Filed: 08/31/2004
• Published: 02/03/2005
• Est. Priority Date: 06/05/2002
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Ahn, Kie Y., Forbes, Leonard
• Granted Patent: US 7,554,161 B2
• Time in Patent Office: Days
• US Class Current: 257/410
• CPC Class Codes: H01L 21/28176 with a treatment, e.g. annealing, after the formation of the definitive gate conductor
• CPC Class Codes: H01L 21/28185 with a treatment, e.g. annealing, after the formation of the gate insulator and before the formation of the definitive gate conductor
• CPC Class Codes: H01L 21/28194 by deposition, e.g. evaporation, ALD, CVD, sputtering, laser deposition H01L21/28202 takes precedence
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/518 the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material

Abstract

A dielectric film containing HfAlO₃ and a method of fabricating such a dielectric film produce a reliable gate dielectric having an equivalent oxide thickness thinner than attainable using SiO₂. A gate dielectric is formed by atomic layer deposition employing a hafnium sequence and an aluminum sequence. The hafnium sequence uses HfCl₄ and water vapor. The aluminum sequence uses either trimethylaluminium, Al(CH₃)₃, or DMEAA, an adduct of alane (AlH₃) and dimethylehtylamine [N(CH₃)₂(C₂H₅)], with distilled water vapor. These gate dielectrics containing a HfAlO₃ film are thermodynamically stable such that the HfAlO₃ film will have minimal reactions with a silicon substrate or other structures during processing.

Claims

1. A transistor comprising:

a body region between a first and a second source/drain region;

a dielectric film containing atomic layer deposited HfAlO₃ disposed on the body region between the first and second source/drain regions; and

a gate coupled to the dielectric film.

2. The transistor of claim 1, wherein the dielectric film includes Al₂O₃ and HfO₂.

3. The transistor of claim 1, wherein the dielectric film is substantially amorphous.

4. The transistor of claim 1, wherein the dielectric film exhibits a dielectric constant in the range from about 9 to about 25.

5. The transistor of claim 1, wherein the dielectric film exhibits an equivalent oxide thickness (t_eq) in the range from about 3 Angstroms to about 12 Angstroms.

6. The transistor of claim 1, wherein the dielectric film exhibits an equivalent oxide thickness (t_eq) of less than 3 Angstroms.

7. The transistor of claim 1, wherein the transistor is configured in a memory.

8. The transistor of claim 1, wherein the transistor is configured in an electronic system.

9. A transistor comprising:

a body region between a first and a second source/drain region;

a film containing HfAlO₃ on the body region between the first and second source/drain regions; and

a gate coupled to the film;

the film formed by atomic layer deposition including;

pulsing a hafnium containing precursor into a reaction chamber containing a substrate;

pulsing a first oxygen containing precursor into the reaction chamber;

pulsing an aluminum containing precursor into a reaction chamber; and

pulsing a second oxygen containing precursor into the reaction chamber.

10. The transistor of claim 9, wherein pulsing a hafnium containing precursor into a reaction chamber includes pulsing a HfCl₄ source gas into the reaction chamber.

11. The transistor of claim 9, wherein pulsing an aluminum containing precursor into the reaction chamber includes pulsing an adduct of alane (AlH₃) and dimethylehtylamine [N(CH₃)₂(C₂H₅)] as a source gas into the reaction chamber.

12. The transistor of claim 9, wherein pulsing an aluminum containing precursor into the reaction chamber includes pulsing a trimethylaluminium source gas into the reaction chamber.

13. A memory having a memory array comprising:

a number of access transistors, each access transistor including a gate coupled to a film containing HfAlO₃, the film formed on a body region between a first and a second source/drain regions;

a number of word lines coupled to a number of the gates of the number of access transistors;

a number of source lines coupled to a number of the first source/drain regions of the number of access transistors; and

a number of bit lines coupled to a number of the second source/drain regions of the number of access transistors;

the film formed by atomic layer deposition including;

pulsing a hafnium containing source gas into a reaction chamber containing a substrate;

pulsing an aluminum containing source gas into the reaction chamber.

14. The memory of claim 13, wherein pulsing a hafnium containing source gas into a reaction chamber includes pulsing a HfCl₄ source gas into the reaction chamber.

15. The memory of claim 13, wherein pulsing an aluminum containing source gas into the reaction chamber includes pulsing an adduct of alane (AlH₃) and dimethylehtylamine [N(CH₃)₂(C₂H₅)] as a source gas into the reaction chamber.

16. The memory of claim 13, wherein pulsing an aluminum containing source gas into the reaction chamber includes pulsing a trimethylaluminium source gas into the reaction chamber.

17. A memory having a memory array comprising:

a number of access transistors, each access transistor including a gate coupled to a film containing atomic layer deposited HfAlO₃, the film disposed on a body region between a first and a second source/drain regions;

a number of word lines coupled to a number of the gates of the number of access transistors;

a number of source lines coupled to a number of the first source/drain regions of the number of access transistors; and

a number of bit lines coupled to a number of the second source/drain regions of the number of access transistors.

18. The memory of claim 17, wherein the film exhibits a dielectric constant in the range from about 9 to about 25.

19. The memory of claim 17, wherein the film exhibits an equivalent oxide thickness (t_eq) in the range from about 3 Angstroms to about 12 Angstroms.

20. An electronic system comprising:

a processor;

a memory, the memory having an array including;

a number of access transistors, each access transistors having a gate coupled to a film containing HfAlO₃, the film formed on a body region between a first and a second source/drain regions;

a number of word lines coupled to a number of the gates of the number of access transistors;

a number of source lines coupled to a number of the first source/drain regions of the number of access transistors;

a number of bit lines coupled to a number of the second source/drain regions of the number of access transistors; and

a system bus that couples the processor to the memory array;

the HfAlO₃ formed by atomic layer deposition including;

pulsing a hafnium containing source gas into a reaction chamber containing a substrate; and

pulsing an aluminum containing source gas into a reaction chamber.

21. The electronic system of claim 20, wherein pulsing a hafnium containing source gas into a reaction chamber includes pulsing a HfCl₄ source gas into the reaction chamber.

22. The electronic system of claim 20, wherein pulsing an aluminum containing source gas into the reaction chamber includes pulsing an adduct of alane (AlH₃) and dimethylehtylamine [N(CH₃)₂(C₂H₅)] as a source gas into the reaction chamber.

23. The electronic system of claim 20, wherein pulsing an aluminum containing source gas into the reaction chamber includes pulsing a trimethylaluminium source gas into the reaction chamber.

24. An electronic system comprising:

a processor; and

a memory, the memory having an array including;

a number of access transistors, each access transistors having a gate coupled to a film containing atomic layer deposited HfAlO₃, the film disposed on a body region between a first and a second source/drain regions;

a number of word lines coupled to a number of the gates of the number of access transistors;

a number of source lines coupled to a number of the first source/drain regions of the number of access transistors;

a number of bit lines coupled to a number of the second source/drain regions of the number of access transistors; and

a system bus that couples the processor to the memory array.

25. The electronic system of claim 24, wherein the film exhibits a dielectric constant in the range from about 9 to about 25.

26. The electronic system of claim 24, wherein the film exhibits an equivalent oxide thickness (t_eq) in the range from about 3 Angstroms to about 12 Angstroms.