Integrated low k dielectrics and etch stops

• US 20050023694A1
• Filed: 08/24/2004
• Published: 02/03/2005
• Est. Priority Date: 02/11/1998
• Status: Active Grant

• Current Assignee: Betty Tang, Claes H. Bjorkman, David W. Cheung, Dennis Yost, Farhad K. Moghadam, Gerald Yin, Hongqing Shan, Judy H. Huang, Kuowei Liu, Melissa Min Yu, Nasreen Gazala Chapra, Wai-Fan Yau, Yunsang Kim
• Original Assignee: Betty Tang, Claes H. Bjorkman, David W. Cheung, Dennis Yost, Farhad K. Moghadam, Gerald Yin, Hongqing Shan, Judy H. Huang, Kuowei Liu, Melissa Min Yu, Nasreen Gazala Chapra, Wai-Fan Yau, Yunsang Kim
• Inventors: Huang, Judy H., Kim, Yunsang, Yau, Wai-Fan, Yin, Gerald, Yost, Dennis, Shan, Hongqing, Liu, Kuowei, Moghadam, Farhad K., Chapra, Nasreen Gazala, Yu, Melissa Min, Bjorkman, Claes H., Cheung, David W., Tang, Betty
• Granted Patent: US 7,227,244 B2
• Time in Patent Office: Days
• US Class Current: 257/758
• CPC Class Codes: C23C 16/401 containing silicon
• CPC Class Codes: H01L 21/02126 the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
• CPC Class Codes: H01L 21/022 the layer being a laminate, i.e. composed of sublayers, e.g. stacks of alternating high-k metal oxides adhesion layers or buffer layers H01L21/02304, H01L21/02362
• CPC Class Codes: H01L 21/02208 the precursor containing a compound comprising Si
• CPC Class Codes: H01L 21/02211 the compound being a silane, e.g. disilane, methylsilane or chlorosilane
• CPC Class Codes: H01L 21/02274 in the presence of a plasma [PECVD]
• CPC Class Codes: H01L 21/02304 formation of intermediate layers, e.g. buffer layers, layers to improve adhesion, lattice match or diffusion barriers
• CPC Class Codes: H01L 21/31116 by dry-etching
• CPC Class Codes: H01L 21/31138 by dry-etching
• CPC Class Codes: H01L 21/3121 Layers comprising organo-silicon compounds
• CPC Class Codes: H01L 21/31612 on a silicon body
• CPC Class Codes: H01L 21/31633 Deposition of carbon doped silicon oxide, e.g. SiOC
• CPC Class Codes: H01L 21/76801 characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
• CPC Class Codes: H01L 21/76802 by forming openings in dielectrics
• CPC Class Codes: H01L 21/76807 for dual damascene structures
• CPC Class Codes: H01L 21/76829 characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
• CPC Class Codes: H01L 21/76835 Combinations of two or more different dielectric layers having a low dielectric constant H01L21/76832 takes precedence

Abstract

A method of depositing and etching dielectric layers having low dielectric constants and etch rates that vary by at least 3:1 for formation of horizontal interconnects. The amount of carbon or hydrogen in the dielectric layer is varied by changes in deposition conditions to provide low k dielectric layers that can replace etch stop layers or conventional dielectric layers in damascene applications. A dual damascene structure having two or more dielectric layers with dielectric constants lower than about 4 can be deposited in a single reactor and then etched to form vertical and horizontal interconnects by varying the concentration of a carbon:oxygen gas such as carbon monoxide. The etch gases for forming vertical interconnects preferably comprises CO and a fluorocarbon, and CO is preferably excluded from etch gases for forming horizontal interconnects.

Claims

1. A structure, comprising:

a substrate;

a first dielectric layer comprising carbon adjacent the substrate; and

a second dielectric layer comprising carbon adjacent the first dielectric layer, wherein the second dielectric layer has a higher carbon concentration than the first dielectric layer.

2. The structure of claim 1, wherein the substrate has a silicon nitride surface layer adjacent the first dielectric layer.

3. The structure of claim 1, further comprising a third dielectric layer comprising carbon adjacent the second dielectric layer.

4. The structure of claim 1, wherein the second dielectric layer contains at least about 5% carbon by atomic weight.

5. The structure of claim 4, wherein the first dielectric layer contains less than two-thirds of the carbon contained in the second dielectric layer.

6. The structure of claim 4, wherein the first dielectric layer contains less than half of the carbon contained in the second dielectric layer.

7. The structure of claim 1, wherein the second dielectric layer further comprises silicon.

8. A structure, comprising:

a substrate;

a first low k dielectric layer comprising silicon, carbon, and hydrogen adjacent the substrate; and

a second low k dielectric layer comprising silicon, carbon, and hydrogen adjacent the first low k dielectric layer, wherein the second low k dielectric layer has a higher carbon concentration than the first low k dielectric layer.

9. The structure of claim 8, wherein the substrate has a silicon nitride surface layer adjacent the first low k dielectric layer.

10. The structure of claim 8, further comprising a third dielectric layer adjacent the second low k dielectric layer.

11. The structure of claim 10, wherein the third dielectric layer comprises carbon.

12. The structure of claim 8, wherein the first and second low k dielectric layers further comprise oxygen.

13. The structure of claim 8, wherein the second low k dielectric layer contains at least about 5% carbon by atomic weight.

14. The structure of claim 13, wherein the first low k dielectric layer contains less than two-thirds of the carbon contained in the second low k dielectric layer.

15. A structure, comprising:

a substrate;

a first dielectric layer comprising carbon adjacent the substrate; and

a second dielectric layer comprising carbon adjacent the first dielectric layer, wherein the second dielectric layer has a higher carbon concentration than the first dielectric layer and the first and second dielectric layer have a first interconnect formed therein.

16. The structure of claim 15, wherein the first interconnect is filled with a conductive material.

17. The structure of claim 15, wherein the first dielectric layer and the second dielectric layer further comprise silicon.

18. The structure of claim 15, further comprising a third dielectric layer comprising carbon adjacent the second dielectric layer.

19. The structure of claim 18, wherein the third dielectric layer comprises a second interconnect.

20. The structure of claim 15, wherein the substrate comprises a layer having a conductive feature formed therein.