Selective electroless-plated copper metallization

• US 20050023699A1
• Filed: 08/30/2004
• Published: 02/03/2005
• Est. Priority Date: 01/18/2000
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Ahn, Kie Y., Forbes, Leonard
• Granted Patent: US 7,262,505 B2
• Time in Patent Office: Days
• US Class Current: 257/762
• CPC Class Codes: H01L 21/288 from a liquid, e.g. electrolytic deposition
• CPC Class Codes: H01L 21/7682 the dielectric comprising air gaps
• CPC Class Codes: H01L 21/76852 the layer also covering the sidewalls of the conductive structure
• CPC Class Codes: H01L 21/76874 for electroless plating
• CPC Class Codes: H01L 21/76879 by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating plating on semiconductors in general H01L21/288
• CPC Class Codes: H01L 21/76885 By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
• CPC Class Codes: H01L 23/4821 Bridge structure with air gap
• CPC Class Codes: H01L 23/5222 Capacitive arrangements or effects of, or between wiring layers other capacitive arrangements H01L23/642
• CPC Class Codes: H01L 23/53238 Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

Structures and methods are provided which include a selective electroless copper metallization. The present invention includes a novel methodology for forming copper vias on a substrate, including depositing a thin film seed layer of Palladium (Pd) or Copper (Cu) on a substrate to a thickness of less than 15 nanometers (nm). A number of via holes is defined above the seed layer. A layer of copper is deposited over the seed layer using electroless plating to fill the via holes to a top surface of the patterned photoresist layer. The method can be repeated any number of times, forming second, third and fourth layers of copper. The photoresist layers along with the seed layers in other regions can then be removed, such as by oxygen plasma etching, such that a chemical mechanical planarization process is avoided.

Claims

1. An integrated circuit, comprising:

at least one semiconductor device formed in a substrate;

a first number of seed layers including a thin film of Palladium (Pd) or Copper formed on a number of portions of the at least one semiconductor device;

a number of copper vias formed above and contacting the first number of seed layers;

a second number of seed layers including a thin film of Palladium (Pd) or Copper formed on the number of copper vias; and

a number of conductor metal lines formed above and contacting second number of seed layers.

2. The integrated circuit of claim 1, wherein the integrated circuit further includes a thin diffusion barrier covering the number of copper vias, the number of conductor metal lines, and the first and the second number of seed layers.

3. The integrated circuit of claim 2, wherein the thin diffusion barrier has a thickness of less than 8.0 nanometers (nm).

4. The integrated circuit of claim 1, wherein the first number of seed layers have a thickness of less than 15 nanometers (nm).

5. The integrated circuit of claim 1, wherein the first number of seed layers includes a first number of seed layers having a discontinuous island structure.

6. The integrated circuit of claim 1, wherein the number of conductor metal lines includes a number of copper metal lines.

7. An integrated circuit, comprising:

a substrate including at least one transistor;

a first number of seed layers including a thin film of Palladium (Pd) or Copper having a thickness of less than 15 nanometers (nm), formed on a source and a drain region of the at least one transistor;

a number of copper vias formed above and contacting the first number of seed layers;

a second number of seed layers including a thin film of Palladium (Pd) or Copper formed on the number of copper vias; and

a number of copper metal lines formed above and contacting the number of second number of seed layers.

8. The integrated circuit of claim 7, wherein the integrated circuit further includes a thin diffusion barrier, having a thickness of less than 8.0 nanometers (nm), covering the number of copper vias, the number of copper metal lines, and the first and the second number of seed layers.

9. The integrated circuit of claim 8, wherein the thin diffusion barrier includes a graded composition of Tungsten Silicon Nitride (WSi_xN_y), and wherein x varies from 2.0 to 2.5.

10. The integrated circuit of claim 7, wherein the second number of seed layers includes a second number of seed layers having a discontinuous island structure with an island thickness in the range of 3 to 10 nanometers.

11. An integrated circuit, comprising:

at least one semiconductor device formed in a substrate;

a first number of seed layers including a thin film of Palladium (Pd) or Copper, having a discontinuous island structure which has a thickness in the range of 3 to 10 nanometers, formed on a number of portions of the at least one semiconductor device;

a number of copper vias formed above and contacting the first number of seed layers;

a second number of seed layers including a thin film of Palladium (Pd) or Copper formed on the number of copper vias;

a number of copper metal lines formed above and contacting the number of second number of seed layers; and

a thin diffusion barrier, having a thickness of less than 8.0 nanometers, covering the number of copper vias, the number of copper metal lines, and the first and the second number of seed layers.

12. The integrated circuit of claim 11, wherein the thin diffusion barrier includes a graded composition of Tungsten Silicon Nitride (WSi_xN_y), and wherein x varies from 2.0 to 2.5.

13. The integrated circuit of claim 11, wherein the second number of seed layers includes a second number of seed layers having a discontinuous island structure with an island thickness in the range of 3 to 10 nanometers.

14. The integrated circuit of claim 11, wherein the thin diffusion barrier has a thickness in the range of 2.0 to 6.0 nanometers.

15. A multilayer copper wiring structure, comprising:

at least one semiconductor device formed in a substrate;

a first number of seed layers including a thin film of Palladium (Pd) or Copper formed on a number of portions of the at least one semiconductor device;

a first level of copper vias formed above and contacting the first number of seed layers;

a second number of seed layers including a thin film of Palladium (Pd) or Copper formed on the first level of copper vias;

a first level of copper metal lines formed above and contacting second number of seed layers;

a third number of seed layers including a thin film of Palladium (Pd) or Copper formed on the first level of copper metal lines;

a second level of copper vias formed above and contacting the third number of seed layers;

a fourth number of seed layers including a thin film of Palladium (Pd) or Copper formed on the second level of copper vias; and

a second level of copper metal lines formed above and contacting fourth number of seed layers.

16. The multilayer copper wiring structure of claim 15, wherein the structure further includes a thin diffusion barrier, having a thickness of less than 8.0 nanometers (nm), covering the first and the second level of copper vias, the first and the second level of copper metal lines, and the first, second, third, and fourth number of seed layers.

17. The multilayer copper wiring structure of claim 15, wherein the thin diffusion barrier includes a graded composition of Tungsten Silicon Nitride (WSi_xN_y), and wherein x varies from 2.0 to 2.5.

18. The multilayer copper wiring structure of claim 15, wherein the first, second, third, and fourth number of seed layers include a discontinuous island structure with an island thickness in the range of 3 to 10 nanometers.

19. A multilayer copper wiring structure, comprising:

a substrate including at least one transistor;

a first number of seed layers including a thin film of Palladium (Pd) or Copper, having a thickness of less than 15 nanometers (nm), formed on a source and a drain region of the at least one transistor;

a first level of copper vias formed above and contacting the first number of seed layers;

a second number of seed layers including a thin film of Palladium (Pd) or Copper, having a thickness of less than 15 nanometers (nm), formed on the first level of copper vias;

a first level of copper metal lines formed above and contacting second number of seed layers;

a third number of seed layers including a thin film of Palladium (Pd) or Copper, having a thickness of less than 15 nanometers (nm), formed on the first level of copper metal lines;

a second level of copper vias formed above and contacting the third number of seed layers;

a fourth number of seed layers including a thin film of Palladium (Pd) or Copper, having a thickness of less than 15 nanometers (nm), formed on the second level of copper vias;

a second level of copper metal lines formed above and contacting fourth number of seed layers; and

a thin diffusion barrier, having a thickness of less than 8.0 nanometers, covering the first and the second level of copper vias, the first and the second level of copper metal lines, and the first, second, third, and fourth number of seed layers.

20. The multilayer copper wiring structure of claim 19, wherein the thin diffusion barrier includes a graded composition of Tungsten Silicon Nitride (WSi_xN_y), and wherein x varies from 2.0 to 2.5.

21. The multilayer copper wiring structure of claim 19, wherein the first, second, third, and fourth number of seed layers include a discontinuous island structure with an island thickness in the range of 3 to 10 nanometers.

22. The multilayer copper wiring structure of claim 19, wherein the thin diffusion barrier has a thickness in the range of 2.0 to 6.0 nanometers.

23. An integrated circuit, comprising:

a semiconductor substrate having a top surface including at least one transistor structure, and a patterned insulator layer having a predetermined vertical thickness overlaying the at least one transistor having openings to access selected portions of the at least one transistor;

a first seed material forming a discontinuous layer covering the patterned insulator layer and discontinuously covering the selected portions of the at least one transistor;

a first level of conductive material covering a selected portion of the first seed layer including at least a portion of the first level of conductive material filling the openings in the patterned insulator layer, the first level of conductive material extending above the predetermined vertical thickness of the patterned insulator layer;

a second seed material forming a discontinuous layer covering at least a top surface of the first level of conductive material;

a second level of conductive material covering at least a portion of the top surface of the first level of conductive material, and not contacting any portion of the patterned insulator layer;

a third seed material forming a discontinuous layer covering at least a top surface of the second level of conductive material;

a third level of conductive material covering at least a portion of the top surface of the second level of conductive material, and not contacting any portion of the patterned insulator layer or the first conductive layer;

a fourth seed material forming a discontinuous layer covering at least a top surface of the third level of conductive material; and

a fourth level of conductive material covering at least a portion of the top surface of the third level of conductive material, and not contacting any portion of the patterned insulator layer, the first conductive layer, or the second conductive layer.

24. The integrated circuit of claim 23 further comprising the first seed layer having an average thickness in the range of 3 to 10 nanometers.

25. The integrated circuit of claim 23 further comprising the first level of conductive material includes a diffusion barrier having a thickness of less than 8 nanometers.

26. The integrated circuit of claim 25 further comprising the diffusion barrier includes a graded composition of Tungsten Silicon Nitride (WSixNy).

27. The integrated circuit of claim 26 further comprising the value of x varies from 20. to 2.5.

28. The integrated circuit of claim 23 further comprising the second level of conductive material includes a diffusion barrier having a thickness of less than 8 nanometers.

29. The integrated circuit of claim 23 further comprising the first level of conductive material forms at least one substantially vertical pillar extending in a vertical direction above the level of the patterned insulator layer.

30. The integrated circuit of claim 23 further comprising the second level of conductive material forms horizontal air bridges between selected ones of the at least one substantially vertical pillars formed of the first conductive material.

31. The integrated circuit of claim 23 further comprising the third level of conductive material forms at least one substantially vertical pillar extending in a vertical direction above the level of the patterned insulator layer and above the level of the second level of conductive material.

32. The integrated circuit of claim 31 further comprising the fourth level of conductive material forms horizontal air bridges between selected ones of the at least one substantially vertical pillars formed of the third conductive material.

33. The integrated circuit of claim 23 further comprising the third level of conductive material includes a diffusion barrier having a thickness of less than 8 nanometers.

34. The integrated circuit of claim 23 further comprising the fourth level of conductive material includes a diffusion barrier having a thickness of less than 8 nanometers.