Control systems and methods

• US 20050023996A1
• Filed: 07/30/2003
• Published: 02/03/2005
• Est. Priority Date: 07/30/2003
• Status: Active Grant

• Current Assignee: Google LLC (Alphabet Inc.)
• Original Assignee: Colorado Vnet
• Inventors: Hesse, Scott, Adamson, Hugh P.
• Granted Patent: US 7,170,238 B2
• Time in Patent Office: Days
• US Class Current: 315/293
• CPC Class Codes: H05B 47/155 Coordinated control of two or more light sources
• CPC Class Codes: H05B 47/175 by remote control

Abstract

Control systems and methods. An embodiment of control system may comprise a processor for receiving control signals from at least one input device when linked thereto. Computer-readable program code is provided at the processor for generating output signals at the processor based on the control signals. An interface is operatively associated with the processor, the interface at least one regulator based on the output signals generated at the processor.

Claims

1. A method for controlling at least one regulator, comprising:

receiving control signals at a processor;

generating output signals at the processor based on the control signals; and

configuring the at least one regulator based on the output signals.

2. The method of claim 1, further comprising addressing the output signals to the at least one regulator.

3. The method of claim 1, further comprising shutting off a load operatively associated with the at least one regulator.

4. The method of claim 1, wherein configuring the at least one regulator is based on analog signals.

5. The method of claim 1, wherein configuring the at least one regulator is based on digital signals.

6. The method of claim 1, further comprising providing at least one auxiliary power source for configuring the at least one regulator.

7. The method of claim 1, further comprising maintaining the output of the at least one regulator in the event of a power source failure.

8. A control system, comprising:

a processor for receiving control signals from at least one input device when linked thereto;

computer-readable program code for generating output signals at said processor based on the control signals; and

an interface operatively associated with said processor, said interface configuring at least one regulator based on the output signals generated at said processor.

9. The control system of claim 8, wherein said processor is linked to said at least one input device via a CAN bus.

10. The control system of claim 8, wherein said computer-readable program code comprises at least one script.

11. The control system of claim 8, wherein said output signals generated at said processor comprise at least a data component and an address component.

12. The control system of claim 8, wherein said output signals generated at said processor comprise a shutoff signal.

13. The control system of claim 8, wherein the regulator controls at least one gas discharge lamp.

14. The control system of claim 8, wherein said interface converts the output signals generated by said processor to analog voltage signals.

15. The control system of claim 8, wherein said interface converts the output signals generated by said processor to current signals.

16. The control system of claim 8, further comprising program code for converting said interface between voltage-control and current-control modes.

17. The control system of claim 8, wherein said interface configures the at least one regulator by delivering pulse width modulated signals to the at least one regulator.

18. The control system of claim 8, wherein said interface configures the at least one regulator by delivering digital signals to the at least one regulator.

19. The control system of claim 8, further comprising at least one auxiliary power source for providing electrical power to said interface.

20. The control system of claim 8, further comprising an external watchdog timer operatively associated with said processor, said watchdog timer indicating the operational status of said processor.

21. The control system of claim 8, further comprising a dual-mode reset circuit operatively associated with said processor, said reset circuit for resetting said processor.

22. The control system of claim 8, wherein said interface supports a plurality of different types of regulators.

23. The control system of claim 8, wherein said interface further comprises:

a digital to analog converter;

an operational amplifier operatively associated with said digital to analog converter, said operational amplifier increasing control granularity of the at least one regulator.

24. The control system of claim 23, wherein said interface further comprises a field effect transistor operatively associated with said operational amplifier, said field effect transistor changing the functionality of said operational amplifier to a comparator when the processor issues an OFF signal.

25. The control system of claim 23, wherein said interface further comprises a light-emitting diode operatively associated with said field effect transistor, said light-emitting diode indicating the operational status of said interface.

26. A control system, comprising:

processing means for generating output signals based on control signals received from a input device; and

interface means for configuring at least one regulator based on the output signals.

27. The control system of claim 26, further comprising means for converting the output signals to analog signals.

28. The control system of claim 26, further comprising means for providing auxiliary power to said interface means.