Pin electronics interface circuit

• US 20050024041A1
• Filed: 08/31/2004
• Published: 02/03/2005
• Est. Priority Date: 08/17/2001
• Status: Active Grant

• Current Assignee: Xcerra Corporation (COHU Incorporated)
• Original Assignee: NPTest, Inc. (COHU Incorporated)
• Inventors: West, Burnell G.
• Granted Patent: US 6,937,006 B2
• Time in Patent Office: Days
• US Class Current: 324/750.10
• CPC Class Codes: G01R 31/31924 Voltage or current aspects, e.g. driver, receiver
• CPC Class Codes: G01R 31/31926 Routing signals to or from the device under test [DUT], e.g. switch matrix, pin multiplexing

Abstract

A pin electronics circuit for use in automatic test equipment may include a reconfigurable logic device in which different logic configurations may be installed to make measurements according to multiple tests to be applied to a device under test; a level generating circuit coupled to the reconfigurable logic device, and configured to generate a number of test levels and a number of reference levels; and a switching circuit, coupled to the reconfigurable logic device and the level generating circuit, configured to receive the test levels and the reference levels, and controlled by the reconfigurable logic device to selectively apply the test levels to the device under test according to a selected test and to sense levels inputted to or outputted from the device under test by comparing the reference levels generated by the level generating circuit to the levels inputted to our outputted from the device under test.

Claims

1. (canceled)

2. A pin electronics circuit-implemented method for use in automatic test equipment, the method comprising:

generating a plurality of test signals and reference signals;

applying each generated test signal to a corresponding one of a plurality of switches;

driving the switches to select an applied test signal;

applying the selected test signal to a device under test; and

comparing one or more of the generated reference signals to the selected test signal or an output signal from the device under test.

3. The circuit implemented method of claim 2, wherein a non-linear network is configured to be coupled between a buffer and the device under test.

4. The circuit implemented method of claim 2, wherein each of the plurality of switches is a complementary metal oxide semiconducting switch.

5. The circuit implemented method of claim 2, wherein driving the switches to select an applied test signal is based on a plurality of test vector signals outputted from a digital test sequencer.

6. The circuit implemented method of claim 2 further comprising making measurements with a reconfigurable logic device according to tests applied to the device under test.

7. The circuit implemented method of claim 6, wherein the reconfigurable logic device comprises a field programmable gate array.

8. The circuit implemented method of claim 6, wherein the reconfigurable logic device comprises a digital test sequencer and a parametric measurement unit.

9. A pin electronics circuit implemented-method for tse in automatic test equipment, the method comprising:

generating a plurality of test levels and a plurality of reference levels with a level generating circuit coupled to a reconfigurable logic device;

receiving the plurality of test levels and the plurality of reference levels with a switching circuit;

controlling the switching circuit with the reconfigurable logic device to selectively apply the plurality of test levels to the device under test according to a plurality of tests; and

making measurements according to the plurality of tests with the reconfigurable logic device and level generating circuit.

10. The pin electronics circuit of claim 9, wherein the reconfigurable logic device comprises:

a digital test sequencer comprising a plurality of outputs, each output configured to output a test vector, and a plurality of inputs, each input configured to receive a compare signal corresponding to an output from one of a plurality of comparators.

11. The pin electronics circuit implemented method of claim 10, wherein the reconfigurable logic device further comprises:

a parametric measurement unit coupled to the level generating circuit and capable of setting the plurality of test levels and the plurality of reference levels according to the plurality of tests.

12. The pin electronics circuit implemented method of claim 9, wherein the level generating circuit comprises a plurality of digital-to-analog converters.

13. The pin electronics circuit implemented method of claim 9 wherein receiving the plurality of test levels and the plurality of reference levels with a switching circuit comprises:

receiving the test levels, each test level received by a corresponding one of a plurality of switches;

receiving the reference levels, each reference level received by a corresponding one of a plurality comparators, each comparator configured to compare the received reference signal to the selected test signal or an output signal from the device under test.

14. The pin electronics circuit implemented method of claim 9 wherein controlling the switching circuit with the reconfigurable logic device to selectively apply the plurality of test levels to the device under test according to the plurality of tests comprises:

outputting a plurality of test vectors, each test vector outputted from a digital test sequencer to a corresponding one of the operational amplifiers;

driving the plurality of switches to relay the received test level to a buffer in accordance with the plurality of test vectors; and

applying the relayed test level to the device under test with the buffer.

16. The pin electronics circuit implemented method of claim of claim 13 wherein each one of the plurality of switches is a complementary metal oxide semiconducting switch.

15. The pin electronics circuit implemented method of 14, wherein a non-linear network is configured to be coupled between the buffer and the device under test.

17. A method for configuring apin electronics circuit to implement a selected test from a plurality of tests, said method comprising:

selecting a test from a plurality of tests to be applied to a device under test;

setting values for a plurality of test levels and a plurality of reference levels with a parametric measurement unit sequencer according to the selected test;

generating the test levels and reference levels at the set values with a level generating circuit; and

applying selectively the generated test levels to the device under test through a switching circuit controlled by a reconfigurable logic device.

18. The method of claim 17 further comprises sensing the test levels applied to the device under test or output levels outputted from the device under test with one or more comparators and the generated reference levels in response to the selected test from the plurality of tests.

19. The method of claim 18 further comprises measuring the sensed test levels or output levels in response to the selected test from the plurality of tests.

20. The method of claim 19 further comprises outputting a signal corresponding to measurements of the sensed test levels or output levels to a display device.

21. The method of claim 17 wherein the test from a plurality may be a parametric measurement unit current test, a parametric measurement unit voltage test, a leakage test, a continuity test, a VOH test, a VOL test, a IIH test, or a ILL test.

22. The method of claim 17 wherein applying selectively the generated test levels to the device under test through a switching circuit controlled by a reconfigurable logic device comprises:

receiving the generated test levels, each generated test level received by a corresponding one of a plurality of switches according to the selected test of the plurality of tests;

outputting a plurality of test vectors, each test vector outputted from a digital test sequencer to a corresponding one of a plurality of operational amplifiers, according to the selected test of the plurality of tests;

driving the plurality of switches to relay the received test level to a buffer in response to the plurality of test vectors; and

applying the relayed test level to the device under test with the buffer.