Testing apparatus and method for thin film transistor display array

• US 20050024081A1
• Filed: 11/19/2003
• Published: 02/03/2005
• Est. Priority Date: 07/29/2003
• Status: Active Grant

• Current Assignee: Primetech International Corporation
• Original Assignee: Primetech International Corporation
• Inventors: Tien, Hsiao Tung, Kuo, Kuang I.
• Granted Patent: US 7,102,378 B2
• Time in Patent Office: Days
• US Class Current: 324/756.70
• CPC Class Codes: G01R 31/31924 Voltage or current aspects, e.g. driver, receiver
• CPC Class Codes: G09G 3/006 Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays testing individual LED's G01R31/2635; testing lamps G01R31/44; testing of optical features of LCD displays G02F1/1309

Abstract

The present invention discloses a testing circuit and method for thin film transistor display array, for testing the yield of thin film transistor array. The testing circuit comprising: An array tester, a test panel (DUT), a sense amplifier array. The sense amplifier is composed by a plurality of trans- impedance amplifier unit and a plurality of parasitic capacitance discharge circuit unit. Every sense amplifier includes: a trans-impedance amplifier, which is implemented by an operational amplifier, two switches and an operation capacitance, the trans-impedance amplifier is used to form an integrated circuit, the output is transmitted to a sampling/hold circuit via a switch; a parasitic capacitance discharge circuit is used to form a discharge rout for the charge of the parasitic capacitance.

Claims

1. A testing circuit for thin film transistor display array testing, use to test the yield of thin film transistor array, comprising:

An array tester, providing electrical power, testing signal waveform, for analyzing, calculating, storing the testing results;

A device under test (DUT) platform, for holding the thin film transistor array, and providing control signal to the platform and the sense amplifier by the array tester;

A sense amplifier array, for transferring (discharge) the parasitic capacitance of the source line of the thin film transistors and integrating the charge current of the pixel storage capacitor, wherein the improvement comprising;

Said sense amplifier array is composed by a plurality of trans-impedance amplifier unit and a plurality of parasitic capacitance discharge circuit, every sense amplifier including;

A trans-impedance amplifier, is composed by an amplifier, two switches and an operation capacitor;

said operation capacitor feed back the output of the amplifier to the negative input of the amplifier;

a switch connecting to the output and negative input of the operational amplifier, to short circuit the operation capacitor for discharge;

another switch to be the input switch, to connect or disconnect with the pixel storage capacitor;

said trans-impedance amplifier forms an integrated circuit, the output is transmitted to a sampling/hold circuit via an output switch and converted to a digital signal;

A discharge circuit for the parasitic capacitance of the source line of the thin film transistors, composed by an amplifier, two switches and an operation capacitor;

said operation capacitor feed back the output of the amplifier to the negative input of the amplifier;

a switch connecting to the output and negative input of the operational amplifier, to short circuit the operation capacitor for discharge;

another switch to be the input switch, to connect or disconnect with the parasitic capacitance of the source line of the thin film transistors;

a load resistance connecting the output of said operational amplifier to the ground;

said discharge circuit forms a discharge circuit for the parasitic capacitance.

2. A testing circuit as recited in claim 1, wherein said thin film transistor array is liquid crystal display (LCD).panel.

3. A testing circuit as recited in claim 1, wherein said thin film transistor array is organic light emitting diode display (OLED) panel.

4. A testing circuit as recited in claim 1, wherein said thin film transistor array is LCOS (liquid crystal on silicon) panel.

5. A testing circuit as recited in claim 1, wherein said thin film transistor is amorphous thin film transistor.

6. A testing circuit as recited in claim 1, wherein said thin film transistor is poly-Si thin film transistor.

7. A testing circuit as recited in claim 1, wherein said thin film transistor is recrystallized silicon thin film transistor.

8. A testing circuit as recited in claim 1, wherein said amplifier is operational amplifier.

9. A testing circuit as recited in claim 1, wherein said switches are control by the programmable output waveform of said array tester.

10. A testing circuit as recited in claim 1, wherein the capacitance of said operation capacitor of said trans-impedance amplifier is 1 pf to 100 pf.

11. A testing circuit as recited in claim 1, wherein the capacitance of said operation capacitor of said discharge circuit is greater than 10 pf.

12. A testing method for invalid pixel (invisible area) of thin film transistor display array, comprising the steps of:

Charging the pixel storage capacitors of the nth column of the device under test to a charge voltage of V_s, then open circuit the pixel transistors after charging;

Switching ON the short circuit switches of the sense amplifiers and the discharge circuits to discharge the operation capacitors of the sense amplifiers and the discharge circuits;

Switching ON the input switches of the discharge circuits;

switching OFF the short circuit switch to discharge the parasitic capacitance of the thin film transistor (transfer the charge), the transferring time is longer;

Switching ON the input switch of the sense amplifier to start operation of the sense amplifier, integrating the current from the pixel storage capacitor of column n and row k, but do not output the result;

Testing the next pixel (column n and row (k+1)).

14. A testing method as recited in claim 12 or 13, wherein said charging voltage V_s of the pixel capacitors is 2 Volts to 10 Volts.

13. A testing method for valid pixel (visible area) of thin film transistor display array, comprising the steps of:

Charging the pixel storage capacitors of the nth column of the device under test to a charge voltage of V_s, then open circuit the pixel transistors after charging;

Switching ON the short circuit switches of the sense amplifiers and the discharge circuits to discharge the operation capacitors of the sense amplifiers and the discharge circuits;

Switching ON the input switch of the sense amplifier to start operation of the sense amplifier, integrating the current from the pixel storage capacitor of column n and row k, the integrated voltage is V_d;

Switching ON the input switches of the discharge circuits;

switching OFF the short circuit switch to discharge the parasitic capacitance of the thin film transistor (transfer the charge), for the testing of the next pixel, the transferring time is shorter;

Testing the next pixel (column n and row (k+1)).

15. A testing method as recited in claim 13, wherein said integrated voltage V_s is greater than 100 mV.