Method of archiving data

• US 20050024941A1
• Filed: 12/16/2003
• Published: 02/03/2005
• Est. Priority Date: 07/30/2003
• Status: Active Grant

• Current Assignee: Western Digital Israel Limited (Western Digital Corporation)
• Original Assignee: M-Systems Flash Disk Pioneers Ltd. (Western Digital Corporation)
• Inventors: Ronen, Amir, Lasser, Menahem
• Granted Patent: US 6,903,972 B2
• Time in Patent Office: Days
• US Class Current: 365/185.190
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 2211/5641 Multilevel memory having cells with different number of storage levels

Abstract

A method and system for archiving data. The data are classified according to their desired lifetime and then archived in a memory using a storage method whose reliability is in accordance with the desired lifetime. For example, when storing data in the cells of an EPROM, short-term data could be archived using larger programming voltage pulse increments than for long-term data, using a lower target threshold voltage than for long-term data, using wider programming voltage pulses than for long-term data, using higher starting programming voltages than for long-term data, using fewer programming voltage pulses than for long term data, using lower maximum programming voltages than for long term data, or using more levels per cell than for long-term data.

Claims

1. A method of archiving data in a memory, comprising the steps of:

(a) classifying the data according to a desired lifetime thereof, and

(b) archiving the data in the memory using a storage method having a reliability in accordance with said desired lifetime.

2. The method of claim 1, wherein said storage method includes a parameter, a value whereof is set in accordance with said classifying to control said reliability.

3. The method of claim 2, wherein said parameter is a programming voltage pulse increment.

4. The method of claim 2, wherein said parameter is a target threshold voltage.

5. The method of claim 2, wherein said parameter is a programming voltage pulse width.

6. The method of claim 2, wherein said parameter is a starting programming voltage.

7. The method of claim 2, wherein said parameter is a maximum number of programming voltage pulses.

8. The method of claim 2, wherein said parameter is a maximum programming voltage.

9. The method of claim 2, wherein said parameter is a number of levels per cell of the memory.

10. A system for archiving data, comprising:

(a) a mechanism for classifying the data according to a desired lifetime thereof; and

(b) a memory having a controller operative to archive the data in said memory using a storage method having a reliability in accordance with said desired lifetime.

11. The system of claim 10, wherein said mechanism includes a processor for running an application that produces and classifies the data.

12. The system of claim 10, wherein said mechanism includes an input device wherewith a user classifies the data.

13. The system of claim 10, wherein said memory is a non-volatile memory.

14. The system of claim 10, wherein said storage method includes a parameter, a value whereof is set in accordance with said classifying to control said reliability.

15. The system of claim 14, wherein said memory is an EPROM including a plurality of cells.

16. The system of claim 15, wherein said parameter is an increment of a voltage pulse used to program said cells.

17. The system of claim 15, wherein said parameter is a target threshold voltage of said cells.

18. The system of claim 15, wherein said parameter is a width of programming voltage pulses used to program said cells.

19. The system of claim 15, wherein said parameter is a starting voltage used to program said cells.

20. The system of claim 15, wherein said parameter is a maximum number of programming voltage pulses used to program said cells.

21. The system of claim 15, wherein said parameter is a maximum voltage used to program said cells.

22. The system of claim 15, wherein said parameter is a number of programming levels of said cells.