Synchronous flash memory with non-volatile mode register

• US 20050024980A1
• Filed: 08/31/2004
• Published: 02/03/2005
• Est. Priority Date: 05/11/2000
• Status: Active Grant

• Current Assignee: Round Rock Research LLC
• Original Assignee: Micron Technology, Inc.
• Inventors: Roohparvar, Frankie F.
• Granted Patent: US 7,054,992 B2
• Time in Patent Office: Days
• US Class Current: 365/232
• CPC Class Codes: G06F 13/1694 Configuration of memory controller to different memory types
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 7/1045 Read-write mode select circuits
• CPC Class Codes: G11C 7/1072 for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories

Abstract

A synchronous flash memory includes an array of non-volatile memory cells. The memory device has a package configuration that is compatible with an SDRAM. The memory device performs memory access operations using mode data that can be stored in a non-volatile mode register. The mode data can be copied into a volatile mode register. Both the non-volatile and volatile mode register can be edited during operation.

Claims

1. A synchronous non-volatile memory comprising:

an array of non-volatile memory cells;

a memory controller;

a non-volatile mode register having a plurality of bit locations to store pre-determined mode data; and

a volatile mode register coupled in parallel with the non-volatile mode register to receive a copy of the mode data from the non-volatile mode register, the memory controller coupled to the volatile mode register and wherein the memory controller establishes operating settings in response to the mode data in the volatile mode register.

2. The synchronous non-volatile memory of claim 1, wherein the operating settings comprise a standard length of burst read operations that can be performed by the controller in response to a burst read operation command.

3. The synchronous non-volatile memory of claim 1, wherein the operating settings comprise an address-sequencing scheme during burst operations.

4. The synchronous non-volatile memory of claim 1, wherein the operating settings comprise a clock latency value for data read operations.

5. The synchronous non-volatile memory of claim 1, wherein the mode data stored in either the volatile mode register or the non-volatile mode register can be edited.

6. The synchronous non-volatile memory of claim 1, further comprising external address connections, and wherein the mode data is edited using new mode data provided on the address connections.

7. The synchronous non-volatile memory of claim 1, wherein the external address connections are couplable to a processor to edit the mode data stored in either the volatile or non-volatile mode register using the address connections.

8. A method of operating a synchronous non-volatile memory device comprising:

copying mode data from a non-volatile mode register to a volatile mode register prior to accessing the memory device;

initiating a data access operation;

reading the mode data from the volatile mode register; and

controlling the data access operation in response to the mode data.

9. The method of claim 8, wherein the mode data is read from the volatile mode register.

10. The method of claim 8, and further comprising editing the mode data stored in either the volatile or non-volatile mode register.

11. The method of claim 8, and further comprising:

adjusting a clock latency value of the memory device to X in response to the mode data;

receiving a memory read command in synchronization with a first clock signal transition; and

outputting memory data read from non-volatile memory cells on data communication connections in synchronization with a second clock signal transition, wherein the second clock signal transition follows the first clock signal transition.

12. The method of claim 11, wherein X is one, two or three.

13. The method of claim 8, and further comprising:

adjusting a burst length for the memory device to a value of X in response to the mode data;

receiving a memory burst read command;

receiving a first memory address; and

outputting memory data read from non-volatile memory cells communication connections starting at the first memory address and sequentially outputting memory data read from X-1 additional memory address locations.

14. The method of claim 13, wherein X is selected from the group comprising 2, 4, 8 and 256.

15. The method of claim 8, and further comprising:

adjusting an addressing sequence in response to the mode data;

receiving a memory burst read command;

receiving a first memory address;

reading data from a memory location having the first memory address;

generating a second memory address based upon the address sequence;

reading data from the second memory address.

16. The method of claim 15, wherein the address sequence is either sequential or an interleaved sequence.

17. A processing system, comprising:

a processor; and

a synchronous non-volatile memory coupled to the processor and comprising;

an array of non-volatile memory cells;

a memory controller;

a non-volatile mode register having a plurality of bit locations to store pre-determined mode data; and

a volatile mode register coupled in parallel with the non-volatile mode register to receive a copy of the mode data from the non-volatile mode register, the memory controller coupled to the volatile mode register and wherein the memory controller establishes operating settings in response to the mode data in the volatile mode register.

18. The processing system of claim 17, wherein the operating settings comprise a standard length of burst read operations that can be performed by the controller in response to a burst read operation command.

19. The processing system of claim 17, wherein the operating settings comprise an address-sequencing scheme during burst operations.

20. The processing system of claim 17, wherein the operating settings comprise a clock latency value for data read operations.

21. The processing system of claim 17, wherein the mode data stored in either the volatile mode register or the non-volatile mode register can be edited.

22. The processing system of claim 17, further comprising external address connections, and wherein the mode data is edited using new mode data provided on the address connections.

23. The processing system of claim 17, wherein the external address connections are coupled to the processor to edit the mode data stored in either the volatile or non-volatile mode register using the address connections.