Method and apparatus for testing loop pathway integrity in a fibre channel arbitrated loop

• US 20050025060A1
• Filed: 07/12/2004
• Published: 02/03/2005
• Est. Priority Date: 07/16/2003
• Status: Active Grant

• Current Assignee: Marvell Asia Pte Limited (Marvell Technology Group Limited)
• Original Assignee: QLogic Corporation (Marvell Technology Group Limited)
• Inventors: Wen, William J., Allada, Sudhakar V., Fike, John M., Hareski, Patricia E.
• Granted Patent: US 7,388,843 B2
• Time in Patent Office: Days
• US Class Current: 370/248
• CPC Class Codes: H04L 43/0811 by checking connectivity
• CPC Class Codes: H04L 43/50 Testing arrangements

Abstract

A method for performing a fibre channel arbitrated loop integrity test using a fibre channel switch element is provided. The method includes, sending a fibre channel frame through the arbitrated loop; receiving the fibre channel frame after it has traversed through the arbitrated loop; performing a data compare between the fibre channel frame that was sent and the fibre channel frame that is received; detecting internal errors, if any, in the traversed fibre channel loop; and isolating a module that may have generated the error. The switch element includes, a cascade port that is used to couple one fibre channel switch element to another in a loop; and a port that sends a fibre channel frame through the loop and detects internal errors based on the comparison and a isolates a module that may have generated the internal error.

Claims

1. A method for performing a fibre channel arbitrated loop integrity test using a fibre channel switch element, comprising:

sending a fibre channel frame through the arbitrated loop;

receiving the fibre channel frame after it has traversed through the arbitrated loop;

performing a data compare between the fibre channel frame that was sent and the fibre channel frame that is received;

detecting internal errors, if any, in the traversed fibre channel loop; and

isolating a module that may have generated the error.

2. The method of claim 1, detecting inter connection data path errors between fibre channel switch elements, if the frame is received without any internal errors.

3. The method of claim 1, wherein the internal errors are checked in a transmission protocol engine port of the fibre channel switch elements.

4. The method of claim 1, wherein plural fibre channel switch elements are coupled to each other using a cascade port and the fibre channel frame is allowed to traverse through the plural fibre channel switch element.

5. A fibre channel switch element coupled to an arbitrated loop, comprising:

a cascade port that is used to couple one fibre channel switch element to another in a loop; and

a port that sends a fibre channel frame through the loop and a compares the fibre channel frame that was sent and the fibre channel frame that is received;

and detects internal errors based on the comparison and a isolates a module that may have generated the internal error.

6. The fibre channel switch element of claim 5, detects inter-connection data path errors between fibre channel switch elements, if the frame is received without any internal errors.

7. A system for performing integrity tests in a fibre channel arbitrated loop, comprising:

a fibre channel switch element including a host port, a cascade port, a generic port for performing diagnostic services, wherein plural fibre channel switch elements are cascaded in a loop and the generic port sends a fibre channel frame through the loop and a compares the fibre channel frame that was sent and the fibre channel frame that is received;

and detects internal errors based on the comparison and a isolates a module that may have generated the internal error.

8. The system of claim 7, wherein the fibre channel switch element detects inter-connection data path errors between fibre channel switch elements, if the frame is received without any internal errors.