Method and apparatus for performing whole wafer burn-in

• US 20050026311A1
• Filed: 08/26/2004
• Published: 02/03/2005
• Est. Priority Date: 11/16/2000
• Status: Active Grant

• Current Assignee: Optical Communication Products Incorporated (KOCH Industries Incorporated)
• Original Assignee: Optical Communication Products Incorporated (KOCH Industries Incorporated)
• Inventors: Wasserbauer, John, Feld, Stewart A.
• Granted Patent: US 7,138,284 B2
• Time in Patent Office: Days
• US Class Current: 438/14
• CPC Class Codes: G01R 31/2635 Testing light-emitting diodes, laser diodes or photodiodes
• CPC Class Codes: G01R 31/2831 Testing of materials or semi-finished products, e.g. semiconductor wafers or substrates G01R31/318511 takes precedence; testing during manufacture H01L22/00
• CPC Class Codes: G01R 31/2856 Internal circuit aspects, e.g. built-in test features; Test chips; Measuring material aspects, e.g. electro migration [EM]

Abstract

A method and apparatus for burning in a semiconductor wafer having a plurality of active devices utilizes temporary conductive interconnect layers to separately couple at least a portion of the anodes of the active devices together as well as at least a portion of the cathodes of the devices together. A simplified probed pad, having a reduced number of contacts may then be utilized to apply a substantially constant voltage or current to the devices. The temporary conductive interconnect layer may be patterned to include device level resistors or array level resistors that may be used to mitigate the effects of short circuits or open circuits on the processing of the devices.

Claims

1-15. -15. (cancelled).

16. A method for burning in a wafer having an insulator layer formed on one surface and a plurality of active device, each device having a first and second electrode, comprising:

forming a first conductive interconnect layer adjacent said insulator layer;

processing said conductive interconnect layer to one or more first electrode contact traces wherein each of said first electrode common contact traces separately couples together the first electrode of each active device within an array; and

processing said first conductive interconnect layer to form one or more second electrode common contact traces wherein said second electrode contact traces simultaneously couple together the second electrode of at least a portion of said active devices.

17. The method of claim 16 further comprising coupling a first test probe to at least a portion of said first electrode common contact traces, coupling a second test probe to at least a portion of said second electrode common contact traces and simultaneously applying a predetermined current or voltage across said first and second test probes.

18. The method of claim 17 further comprising removing said insulator layer and said conductive interconnect layer.

19. The method of claim 16 further comprising forming a resistor between said one or more first electrode common contact traces and the first electrode of said active devices.

20. The method of claim 19 wherein forming a resistor between said one or more first electrode common contact traces and the first electrode of said active devices comprises processing said first conductive interconnect layer between said one or more first electrode common contact traces and the first electrode of said portion of the active devices.

21. The method of claim 19 wherein processing said first conductive interconnect layer comprises forming a serpentine pattern in the first conductive interconnect layer between said one or more first electrode common contact traces and the first electrode of said active devices.

22. The method of claim 16 further comprising depositing a second insulator layer adjacent said first conductive interconnect layer, forming a first contact adjacent to a first portion of said second insulator layer that simultaneously couples together at least a portion of the first electrode common contact traces of at least a portion of the active devices, forming a second contact adjacent a second portion of said second insulator layer that simultaneously couples together at least a portion of said second electrode common contact traces.

23. The method of claim 22 further comprising coupling a first test probe to said first contact, coupling a second test probe to said second contact and simultaneously applying a predetermined voltage across said contacts.

24. The method of claim 23 further comprising removing said first and second insulator layers, said first conductive interconnect layer and said first and second contacts.

25. The method of claim 22 further comprising forming a resistor between said first contact at least said portion of said first electrode common contact traces.

26. The method of claim 22 further comprising forming a fuse between said first contact at least said portion of said first electrode common contact traces.

27. The method of claim 26 further comprising probing said active devices and blowing fuse associated with failed active devices.

28. The method of claim 27 further comprising coupling a first test probe to said first contact, coupling a second test probe to said second contact and simultaneously applying a predetermined current or voltage across said contacts.

29. The method of claim 28 further comprising removing said first and second insulator layers, said first conductive interconnect layer and said first and second contacts.