Isolation circuit

• US 20050026315A1
• Filed: 08/30/2004
• Published: 02/03/2005
• Est. Priority Date: 06/20/2002
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Cowles, Timothy B., Lunde, Aron T.
• Granted Patent: US 7,378,290 B2
• Time in Patent Office: Days
• US Class Current: 438/18
• CPC Class Codes: G01R 31/2884 using dedicated test connectors, test elements or test circuits on the IC under test G01R31/2855 takes precedence

Abstract

An isolation circuit includes a first pad adapted to receive a control signal and a second pad adapted to receive another signal. A third pad is coupled to a microelectronic die and a device is provided to transfer the other signal from the second pad to the third pad in response to the control signal.

Claims

1. A method of making an isolation circuit, comprising:

forming a first pad adapted to receive a control signal;

forming a second pad adapted to receive another signal;

forming a third pad coupled to a component formed in a microelectronic die; and

forming a device adapted to transfer the other signal from the second pad to the third pad in response to the control signal.

2. The method of claim 1, wherein forming the device comprises forming one of a metal oxide semiconductor (MOS) device, a multiplexor, a conductive jumper, a fuse device and an anti-fuse device.

3. The method of claim 1, wherein forming at least one of the first pad, the second pad and the device includes forming in one of a scribe line of a wafer, a mutant die of a wafer or a sacrifice die of a wafer.

4. The method of claim 1, wherein forming at least one of the first pad, the second pad and the device includes forming on the microelectronic die with the component.

5. A method of making an isolation circuit, comprising:

forming a first pad to receive a signal;

forming a second pad coupled to a component;

forming a first device adapted to transfer the signal from the first pad to the second pad in response to a control signal; and

forming a second device to selectively prevent the first pad from being coupled to the second pad.

6. The method of claim 5, further comprising providing a wireless identification circuit to provide the control signal.

7. The method of claim 5, further comprising forming a control pad coupled to the first device to receive the control signal.

8. A method of making a microelectronic die, comprising:

forming a first pad adapted to receive a control signal;

forming a second pad adapted to receive another signal;

forming a third pad coupled to a component formed on the microelectronic die; and

forming a device adapted to transfer the other signal from the second pad to the third pad in response to the control signal.

9. The method of claim 8, further comprising:

forming a second device adapted to selectively prevent the second pad from being coupled to the third pad during a predetermined use of the microelectronic die.

10. A method of making a microelectronic die, comprising:

forming a first pad to receive a signal;

forming a second pad coupled to a component;

forming a first device adapted to transfer the signal from the first pad to the second pad in response to a control signal; and

forming a second device to selectively prevent the first pad from being coupled to the second pad.

11. A method of making an electronic system, comprising:

forming a processor; and

forming a memory system coupled to the processor, wherein at least one of the processor and the memory system are formed on a microelectronic die including an isolation circuit and wherein forming the isolation circuit includes;

forming a first pad adapted to receive a control signal;

forming a second pad adapted to receive another signal;

forming a third pad coupled to one of the processor and the memory system; and

forming a device adapted to transfer the other signal from the second pad to the third pad in response to the control signal.

12. The method of claim 11, further comprising forming a second device adapted to selectively prevent the second pad from being coupled to the third pad during a predetermined use of the electronic system.

13. A method of making an electronic system, comprising:

forming a processor; and

forming a memory system coupled to the processor, wherein at least one of the processor and the memory system are formed on a microelectronic die including an isolation circuit and wherein forming the isolation circuit includes;

forming a first pad to receive a signal;

forming a second pad coupled to one of the processor and the memory system;

forming a first device adapted to transfer the signal from the first pad to the second pad in response to a control signal; and

forming a second device to selectively prevent the first pad from being coupled to the second pad.

14. A method, comprising:

determining if any microelectronic dies of a plurality of microelectronic dies formed on a semiconductor wafer are defective;

applying a test signal to a test pad associated with each of the microelectronic dies;

operating a device associated with each microelectronic die to couple the test pad to a part pad if the microelectronic die is good, wherein the part pad is connected to the microelectronic die; and

preventing the test signal from being applied to the microelectronic die if the die is defective.

15. The method of claim 14, wherein operating the device comprises one of:

sending a gate signal to operate a MOS transistor;

sending a signal to operate a multiplexor;

forming a conductive jumper; and

operating an anti-fuse device.

16. The method of claim 14, wherein preventing the test signal from being applied to the microelectronic die comprises one of:

sending a gate signal to prevent a MOS transistor from operating;

operating a fuse device; and

operating a multiplexor to prevent the test pad from being coupled to the part pad.

17. The method of claim 14, further comprising:

receiving a radio frequency signal to operate the device if the microelectronic die is good.

18. A method, comprising:

determining if any microelectronic dies of a plurality of microelectronic dies formed on a semiconductor wafer are defective;

applying a test signal to a test pad associated with each of the microelectronic dies;

operating a device associated with each microelectronic die to couple the test pad to a part pad associated with each microelectronic die if the microelectronic die is good, wherein the part pad is connected to the microelectronic die;

preventing the test signal from being applied to the microelectronic die if the die is defective; and

preventing each test pad from being coupled to each associated part pad during a selected use of the microelectronic die.

19. The method of claim 18, wherein the device is an N-channel transistor and wherein preventing each test pad form being coupled to each associated part pad comprises grounding a gate of the N-channel transistor.

20. The method of claim 18, wherein the device is a P-channel transistor and wherein preventing each test pad from being coupled to each associated part pad comprises applying a high signal to a gate of the P-channel transistor.