Buried strap contact for a storage capacitor and method for fabricating it

• US 20050026359A1
• Filed: 06/25/2004
• Published: 02/03/2005
• Est. Priority Date: 06/26/2003
• Status: Active Grant

• Current Assignee: Polaris Innovations Limited (Wi-LAN Inc.)
• Original Assignee: Infineon Technologies AG
• Inventors: Enders, Gerhard, Voigt, Peter
• Granted Patent: US 7,163,857 B2
• Time in Patent Office: Days
• US Class Current: 438/243
• CPC Class Codes: H01L 29/66181 Conductor-insulator-semiconductor capacitors, e.g. trench capacitors
• CPC Class Codes: H01L 29/945 Trench capacitors
• CPC Class Codes: H10B 12/0385 Making a connection between the transistor and the capacitor, e.g. buried strap
• CPC Class Codes: H10B 12/37 the capacitor being at least partially in a trench in the substrate

Abstract

A buried strap contact between a trench capacitor of a memory cell and the subsequently formed selection transistor of the memory cell is fabricated such that the inner capacitor electrode layer is etched back in the trench of the trench capacitor and the uncovered insulator layer is then removed at the trench wall in order to define the region of the buried strap contact area. A liner layer is subsequently deposited in order to cover the inner capacitor electrode layer in the trench and the uncovered trench wall and thus to form a barrier layer. A spacer layer with the material of the inner electrode layer is then formed on the liner layer at the trench wall. Finally, the uncovered liner layer is removed above the inner electrode layer and the trench is filled with the material of the inner electrode layer in order to fabricate the buried strap contact.

Claims

1. A method for fabricating a buried strap contact for a storage capacitor of a memory cell, the storage capacitor being formed in a trench of a semiconductor substrate with an outer electrode layer around a lower region of the trench in the semiconductor substrate, a dielectric intermediate layer embodied on the lower region of the trench wall of the trench, an insulation layer, which is formed in a manner adjoining the dielectric intermediate layer on an upper region of the trench wall of the trench, and an inner electrode layer essentially filling the trench, comprising:

etching back of the inner electrode layer into the trench;

removing the uncovered insulator layer from the trench wall to define buried strap contact areas;

depositing a liner layer to cover the inner electrode layer in the trench and the uncovered trench wall;

forming a spacer layer with the material of the inner electrode layer on the liner layer at the trench wall;

removing the uncovered liner layer from the inner electrode layer in the trench; and

filling the trench with the material of the inner electrode layer.

2. The method as claimed in claim 1, wherein the semiconductor substrate is an Si substrate, the material of the inner electrode layer being poly-Si, and the liner layer comprising Si₃N₄.

3. The method as claimed in claim 1, wherein a thickness of the liner layer is approximately 1 nm.

4. The method as claimed in claim 1, wherein the spacer layer is formed by depositing, in large-area fashion, a layer with the material of the inner electrode layer, which is essentially removed again from horizontal areas by anisotropic etching to uncover the liner layer at the trench bottom.

5. The method as claimed in claim 4, wherein the liner layer is concomitantly removed at the trench bottom during the anisotropic etching back to form the spacer layer.

6. A memory cell having a storage capacitor, which is formed in a trench of a semiconductor substrate with an outer electrode layer around a lower region of the trench in the semiconductor substrate, a dielectric intermediate layer embodied on the lower region of the trench wall of the trench, an insulation layer, which is formed in a manner adjoining the dielectric intermediate layer on an upper region of the trench wall of the trench, and an inner electrode layer essentially filling the trench, and having a selection transistor, which has a first and a second electrode region in the semiconductor substrate, between which an active region is arranged, configured to form a current-conducting channel between the first and second electrode regions in the active region, the inner electrode layer of the storage capacitor being connected to one of the two electrode regions of the selection transistor via a buried strap contact, which is arranged in the trench in a section without an insulation layer at the trench wall directly on the inner electrode layer of the storage capacitor, in a manner isolated from the electrode region of the selection transistor by a liner layer at the trench wall, and comprises the material of the inner electrode layer.

7. The memory cell as claimed in claim 6, wherein the semiconductor substrate is an Si substrate, the material of the inner electrode layer being poly-Si and the liner layer comprising Si₃N₄.

8. The method as claimed in claim 7, wherein a thickness of the liner layer between the buried strap contact on the inner electrode layer of the storage capacitor and the electrode region of the selection transistor being approximately 1 nm.