Method and apparatus on (110) surfaces of silicon structures with conduction in the <110> direction

• US 20050026369A1
• Filed: 08/31/2004
• Published: 02/03/2005
• Est. Priority Date: 08/31/1999
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Forbes, Leonard, Noble, Wendell P., Reinberg, Alan R.
• Granted Patent: US 7,045,880 B2
• Time in Patent Office: Days
• US Class Current: 438/259
• CPC Class Codes: H01L 21/2255 the applied layer comprising oxides only, e.g. P2O5, PSG, H3BO3, doped oxides
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 21/823412 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823481 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823885 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823821
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 29/045 by their particular orientation of crystalline planes
• CPC Class Codes: H01L 29/0657 characterised by the shape of the body
• CPC Class Codes: H01L 29/66787 with a gate at the side of the channel
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7851 with the body tied to the substrate
• CPC Class Codes: H10B 12/053 the transistor being at least partially in a trench in the substrate vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383
• CPC Class Codes: H10B 12/056 the transistor being a FinFET
• CPC Class Codes: Y10S 438/973 Substrate orientation

Abstract

Improved methods and structures are provided that are lateral to surfaces with a (110) crystal plane orientation such that an electrical current of such structures is conducted in the <110> direction. Advantageously, improvements in hole carrier mobility of approximately 50% can be obtained by orienting the structure'"'"'s channel in a (110) plane such that the electrical current flow is in the <110> direction. Moreover, these improved methods and structures can be used in conjunction with existing fabrication and processing techniques with minimal or no added complexity.

Claims

1. A semiconductor device, comprising:

a first conductive n-type region in a trench of a silicon wafer such that the first conductive n-type region is lateral to a trench wall of the trench, wherein the trench wall has a (110) crystal plane orientation;

a second conductive n-type region in the trench such that the second conductive n-type region is lateral to the trench wall; and

a conductive p-type region in the trench such that the conductive p-type region is lateral to the trench wall and located between the first and second conductive n-type regions, wherein the semiconductor device is designed to conduct an electrical current between the first and second conductive p-type regions in a direction parallel to a top surface of the silicon wafer.

2. The semiconductor device of claim 1, wherein the silicon wafer has a top surface having a (100) crystal plane orientation.

3. A semiconductor device, comprising:

a number of trenches formed in a silicon wafer; and

a number of spaced MOSFETs in each trench, wherein each MOSFET includes;

a first conductive p-type region in a trench of the silicon wafer such that the first conductive p-type region is lateral to a trench wall of the trench, wherein the trench wall has a (110) crystal plane orientation;

a second conductive p-type region in the trench such that the second conductive p-type region is lateral to the trench wall; and

a conductive n-type region in the trench such that the conductive n-type region is lateral to the trench wall and between the first and second conductive p-type regions, wherein an electrical current is capable of flowing between the first and second conductive p-type regions in a <

110>

direction.

4. The semiconductor device of claim 3, wherein the silicon wafer includes a bulk silicon material.

5. The semiconductor device of claim 3, wherein the silicon wafer has a top surface with a (100) crystal plane orientation.

6. The semiconductor device of claim 3, wherein each MOSFET includes a gate which opposes the conductive n-type region.

7. The semiconductor device of claim 6, wherein each MOSFET includes a gate oxide separating the gate and the conductive n-type region.

8. The semiconductor device of claim 7, further including a wordline coupling together the gates on each MOSFET in each trench.

9. An electronic system comprising:

a processor; and

an integrated circuit coupled to the processor, wherein the integrated circuit is formed on a silicon wafer, and wherein the silicon wafer includes;

a trench wall having a (110) crystal plane orientation; and

a semiconductor device lateral to the trench wall, wherein the semiconductor device is capable of conducting an electrical current in a <

110>

direction.

10. The electronic system of claim 9, wherein the processor and the integrated circuit are formed on the same silicon wafer

11. The electronic system of claim 9, wherein a top surface of the silicon wafer has a (100) crystal plane orientation.

12. The electronic system of claim 9, wherein the silicon wafer includes a bulk silicon material.

13. The electronic system of claim 9, wherein the semiconductor device includes a p-channel Metal Oxide Semiconductor Field Effect Transistor (p-MOSFET) device.

14. An electronic system comprising:

a processor; and

a semiconductor device coupled to the processor, the semiconductor device including;

a first conductive region of a first type in a trench of a silicon wafer such that the first conductive region of the first type is lateral to a trench wall of the trench, wherein the trench wall has a (110) crystal plane orientation;

a second conductive region of the first type in the trench such that the second conductive region of the first type is lateral to the trench wall; and

a third conductive region of a second type in the trench such that the third conductive region of the second type is lateral to the trench wall and between the first and second conductive regions of the first type, wherein an electrical current is capable of flowing between the first and second conductive regions of the first type in a <

110>

direction.

15. The electronic system of claim 14, wherein the third conductive region of the second type includes a channel of a Metal Oxide Semiconductor Field Effect Transistor (MOSFET) device.

16. The electronic system of claim 14, wherein the first type is an n-type.

17. The electronic system of claim 14, wherein the second type is an p-type.

18. The electronic system of claim 14, wherein the silicon wafer has a top surface having a (100) crystal plane orientation.

19. A semiconductor device, comprising:

a layer of conductive material of a first type;

at least one trench formed in the layer of conductive material, the at least one trench including a trench wall; and

at least one semiconductor device formed laterally to the trench wall, the at least one semiconductor device comprising;

a first conductive region of a second type formed laterally to the trench wall;

a second conductive region of the second type formed laterally to the trench wall; and

a third conductive region of the layer of conductive material disposed laterally to the trench wall and separating the first and second conductive regions to provide a channel to conduct electrical current between the first and second conductive regions.

20. The semiconductor device of claim 19, wherein the first and second conductive regions are formed by at least one of rapid thermal annealing, ion implantation, angled ion implantation, and chemical vapor deposition.

21. The semiconductor device of claim 19, wherein the at least one semiconductor device is one of an n-channel semiconductor device or a p-channel semiconductor device.

22. A semiconductor device, comprising:

a substrate;

a layer of conductive material of a first type formed on the substrate;

at least one trench formed in the layer of conductive material and including trench walls substantially perpendicular to a plane of the substrate; and

at least one semiconductor device formed laterally to at least one of the trench walls, the at least one semiconductor device comprising;

a first conductive region of a second type formed laterally to the at least one trench wall;

a second conductive region of the second type formed laterally to the at least one trench wall; and

a third conductive region of the layer of conductive material disposed laterally to the at least one trench wall and separating the first and second conductive regions to permit electrical current to be conducted between the first and second conductive regions.

23. A semiconductor device, comprising:

a layer of conductive material of a first type;

at least one trench formed in the layer of conductive material, the at least one trench including a trench wall having a (110) crystal plane orientation; and

at least one semiconductor device formed laterally to the trench wall, the at least one semiconductor device comprising;

a first conductive region of a second type formed laterally to the trench wall;

a second conductive region of the second type formed laterally to the trench wall; and

a third conductive region of the layer of conductive material disposed laterally to the trench wall and separating the first and second conductive regions to permit electrical current to be conducted in a <

110>

direction between the first and second conductive regions.

24. A semiconductor device, comprising:

a substrate;

a layer of conductive material of a first type formed on the substrate;

at least one trench formed in the layer of conductive material and including a trench wall substantially perpendicular to a top surface of the substrate and including a (110) crystal plane orientation; and

at least one semiconductor device formed in a plane defined by the trench wall, the at least one semiconductor device comprising;

a first conductive region of a second type formed in the plane of the trench wall;

a second conductive region of the second type formed in the plane of the trench wall; and

a third conductive region of the layer of conductive material disposed in the plane of the trench wall and separating the first and second conductive regions to permit electrical current to be conducted in a <

110>

direction.

25. A semiconductor device, comprising:

a layer of conductive material of a first type;

a plurality of trenches formed in the layer of conductive material, each trench including a trench wall;

at least one semiconductor device formed laterally to the trench wall, the at least one semiconductor device comprising;

a first conductive region of a second type formed laterally to the trench wall;

a second conductive region of the second type formed laterally to the trench wall; and

a third conductive region of the layer of conductive material disposed laterally to the trench wall and separating the first and second conductive regions to provide a channel to conduct electrical current between the first and second conductive regions.

26. A semiconductor device, comprising:

an array of memory elements, each memory element comprising;

a first conductive region of a first type formed laterally in a trench wall;

a second conductive region of the first type formed laterally to the trench wall; and

a third conductive region of a second type disposed laterally to the trench wall and separating the first and second conductive regions to provide a channel to conduct electrical current between the first and second conductive regions; and

a wordline coupled to each memory element.

27. A semiconductor device, comprising:

a first conductive region of a first type formed laterally in a trench wall;

a second conductive region of the first type formed laterally to the trench wall; and

a third conductive region of a second type disposed laterally to the trench wall and separating the first and second conductive regions to provide a channel to conduct electrical current between the first and second conductive regions.

28. A semiconductor device, comprising:

a first conductive region of a first type formed laterally to a trench wall having a (110) crystal plane orientation;

a second conductive region of the first type formed laterally to the trench wall; and

a third conductive region of a second type disposed laterally to the trench wall and separating the first and second conductive regions to permit electrical current to be conducted in a <

110>

direction between the first and second conductive regions.

29. A semiconductor device, comprising:

a layer of conductive material of a first type formed on a substrate;

at least one trench formed in the layer of conductive material and including a trench wall substantially perpendicular to a top surface of the substrate and including a (110) crystal plane orientation;

a first conductive region of a second type formed in a plane of the trench wall;

a second conductive region of the second type formed in the plane of the trench wall; and

a third conductive region of the layer of conductive material disposed in the plane of the trench wall and separating the first and second conductive regions to permit electrical current to be conducted in a <

110>

direction.

30. An electronic system, comprising:

a processor; and

a semiconductor device coupled to the processor, wherein the semiconductor device comprises;

a first conductive region of a first type formed laterally in a trench wall;

a second conductive region of the first type formed laterally to the trench wall; and

a third conductive region of a second type disposed laterally to the trench wall and separating the first and second conductive regions to provide a channel to conduct electrical current between the first and second conductive regions.

31. An electronic system, comprising:

a processor; and

a semiconductor device coupled to the processor, wherein the semiconductor device comprises;

a first conductive region of a first type formed laterally to a trench wall having a (110) crystal plane orientation;

a second conductive region of the first type formed laterally to the trench wall; and

a third conductive region of a second type disposed laterally to the trench wall and separating the first and second conductive regions to permit electrical current to be conducted in a <

110>

direction between the first and second conductive regions.

32. An electronic system, comprising:

a processor; and

a memory device coupled to the processor, the memory device comprising;

a layer of conductive material of a first type;

at least one trench formed in the layer of conductive material, the at least one trench including a trench wall;

at least one memory element formed laterally to the at least one trench wall, the at least one memory element comprising;

a first conductive region of a second type formed laterally to the trench wall;

a second conductive region of the second type formed laterally to the trench wall; and

a third conductive region of the layer of conductive material disposed laterally to the trench wall and separating the first and second conductive regions to provide a channel to conduct electrical current between the first and second conductive regions.

33. An electronic system, comprising:

a processor; and

a memory device coupled to the processor, the memory device including an array of memory elements, each memory element comprising;

a first conductive region of a first type formed laterally to a trench wall having a (110) crystal plane orientation;

a second conductive region of the first type formed laterally to the trench wall; and

a third conductive region of a second type disposed laterally to the trench wall and separating the first and second conductive regions to permit electrical current to be conducted in a <

110>

direction between the first and second conductive regions.

34. An electronic system, comprising:

a processor; and

a memory device couple to the processor, the memory device comprising;

an array of memory element, each memory element comprising;

a layer of conductive material of a first type formed on a substrate;

at least one trench formed in the layer of conductive material and including a trench wall substantially perpendicular to a top surface of the substrate and including a (110) crystal plane orientation;

a first conductive region of a second type formed in a plane of the trench wall;

a second conductive region of the second type formed in the plane of the trench wall; and

a third conductive region of the layer of conductive material disposed in the plane of the trench wall and separating the first and second conductive regions to permit electrical current to be conducted in a <

110>

direction.