Process for producing a plurality of gate stacks which are approximately the same height and equidistant on a semiconductor substrate

• US 20050026407A1
• Filed: 08/12/2004
• Published: 02/03/2005
• Est. Priority Date: 03/28/2002
• Status: Active Grant

• Current Assignee: Polaris Innovations Limited (Wi-LAN Inc.)
• Original Assignee: Qimonda AG (Infineon Technologies AG)
• Inventors: Wich-Glasen, Andreas, Popp, Martin
• Granted Patent: US 7,129,155 B2
• Time in Patent Office: Days
• US Class Current: 438/587
• CPC Class Codes: H01L 21/26506 in group IV semiconductors
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 21/28247 passivation or protection of the electrode, e.g. using re-oxidation
• CPC Class Codes: H01L 21/76888 By rendering at least a portion of the conductor non conductive, e.g. oxidation
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665

Abstract

Process for producing a plurality of gate stacks approximately the same height and equidistant on a semiconductor substrate. The process includes providing a gate dielectric on the semiconductor substrate and applying and patterning at least a first layer and a second layer, above the first layer, to the gate dielectric to produce the gate stacks. An oblique implantation of an oxidation-inhibiting implantation species is carried out into two opposite, uncovered side faces of the second of the gate stacks, with respectively adjacent gate stacks serving to shadow the uncovered side faces of the first layer of the gate stacks. Oxidation to simultaneously form a first oxide layer on uncovered side faces of the first layer of the gate stacks and a second oxide layer on uncovered side faces of the second layer of the gate stacks is carried out, the thickness of the first oxide layer being greater than the thickness of the second oxide layer.

Claims

1. A process for producing a plurality of gate stacks which are approximately the same height and equidistant on a semiconductor substrate, comprising the steps of:

(a) providing a gate dielectric on the semiconductor substrate;

(b) applying and patterning at least a first layer and a second layer, above the first layer, to the gate dielectric in order to produce the gate stacks;

(c) carrying out an oblique implantation of an oxidation-inhibiting implantation species into two opposite, uncovered side faces of the second of the gate stacks, with respectively adjacent gate stacks serving to shadow the uncovered side faces of the first layer of the gate stacks; and

(d) carrying out oxidation to simultaneously form a first oxide layer on uncovered side faces of the first layer of the gate stacks, and a second oxide layer on uncovered side faces of the second layer of the gate stacks, the thickness of the first oxide layer being greater than the thickness of the second oxide layer.

2. The process as claimed in claim 1, wherein the oxidation is a wet or dry oxidation.

3. The process as claimed in claim 1 wherein the first layer is a polysilicon layer and the second layer is a metal silicide layer, in particular a tungsten silicide layer.

4. The process as claimed in claim 1, wherein to produce the gate stacks, a first layer, a second layer above the first layer and a third layer above the second layer are applied to the gate dielectric and patterned.

5. The process as claimed in claim 4, wherein the third layer is a silicon nitride layer.

6. The process as claimed in claim 1, wherein silicon nitride side wall spacers are formed over the gate stacks (GS1, GS2, GS3) together with the first and second oxide layers.

7. The process as claimed in claim 1, wherein the implantation species is nitrogen.