Programmable random bit source

• US 20050027765A1
• Filed: 08/01/2003
• Published: 02/03/2005
• Est. Priority Date: 08/01/2003
• Status: Active Grant

• Current Assignee: Steven E. Wells
• Original Assignee: Steven E. Wells
• Inventors: Wells, Steven E.
• Granted Patent: US 7,177,888 B2
• Time in Patent Office: Days
• US Class Current: 708/250
• CPC Class Codes: H03K 3/017 Adjustment of width or dutycycle of pulses pulse width modulation H03K7/08 ; to maintain energy constant H03K3/015
• CPC Class Codes: H03K 3/84 Generating pulses having a predetermined statistical distribution of a parameter, e.g. random pulse generators
• CPC Class Codes: H03K 5/1565 the output pulses having a constant duty cycle

Abstract

A method of producing a uniform duty cycle output from a random bit source. The method includes testing the duty cycle of said random bit source; varying the output voltage of a voltage source if the duty cycle is not substantially fifty percent; and iteratively altering the output voltage of the voltage source until said duty cycle is substantially fifty percent.

Claims

1. A method comprising:

testing a duty cycle of a random bit source;

varying an output voltage of a voltage source if the duty cycle has not substantially reached a first threshold; and

iteratively altering the output voltage of the voltage source until the duty cycle has not substantially reached the first threshold.

2. The method of claim 1 further comprising:

periodically latching a high frequency signal in response to a low frequency signal; and

outputting one or more binary digits corresponding to a voltage level of the latching high frequency signal.

3. The method of claim 1 wherein varying the output voltage of the voltage circuit further comprises updating a threshold voltage of a flash memory cell in the voltage circuit.

4. The method of claim 1 wherein varying the output voltage of the voltage circuit further comprises:

varying an input current to a non-inverting input of a differential amplifier to produce a first input voltage; and

varying an input current to an inverting input of the differential amplifier to produce a second input voltage.

5. The method of claim 1 wherein varying the output voltage of the voltage circuit further comprises altering the number of transistors in the voltage circuit determining the output voltage.

6. The method of claim 1 wherein the method of producing a uniform duty cycle output from a random bit source is used in a random number generator operable to produce random binary numbers for use in a cryptographic system for secure communications between a plurality of computers in a network.

25. The method of claim 1 wherein the first threshold is fifty percent.

7. A programmable random bit source comprising:

a latch having a data input and a clock input;

a first oscillator coupled to the data input of the latch, the first oscillator to output a first oscillating signal; and

a second oscillator to output a second oscillating signal having a frequency slower than a frequency of the first oscillating signal.

8. The programmable random bit source of claim 7 further comprising a programmable voltage source coupled to a bias input of the latch.

9. The programmable random bit source of claim 8 wherein the programmable voltage source comprises:

a first flash memory cell;

a second flash memory cell; and

a differential amplifier having a first input coupled to the first flash memory cell, and a second input coupled to the second flash memory cell.

10. The programmble random bit source of claim 7 wherein the programmable voltage source comprises;

a first resistor;

a second resistor; and

a differential amplifier having a first input coupled to the first resistor, and a second input coupled to the second resistor.

11. The programmable random bit source of claim 7 wherein the programmable voltage source comprises a logic gate having:

a first pull-up transistor;

a first pull-down transistor; and

a second pull-up transistor coupled in parallel with the first pull-up transistor.

12. The programmable randon bit source of claim 11 wherein the logic gate further comprises means for selectivity enabling the second pull-up transistor.

13. The programmable randon bit source of claim 7 wherein the programmable voltage source comprises a logic gate having:

a first pull-up transistor;

a first pull-down transistor; and

a second pull-down transistor coupled in parallel with the first pull-down transistor.

14. The programmable random bit source of claim 13 wherein the logic gate further comprises means for selectively enabling the second pull-down transistor.

15. The programmable random bit source of claim 7 wherein the latch has an adjustable trip point.

16. The programmable random bit source of claim 15 further comprising a programmable voltage source coupled to a bias input of the latch, wherein the adjustable trip point of the latch is alterable by a voltage output by the programmable voltage source.

17. A programmable random bit source comprising:

a latch having a data input and a bias input;

a programmable voltage source coupled to the bias input of the latch;

a comparator having an output coupled to the data input of the latch;

a resistor-inductor-capacitor circuit coupled to an input of the comparator; and

a noise source coupled to the resistor-inductor-capacitor circuit.

18. The programmable random bit source of claim 17 wherein the latch has an alterable trip point.

19. A digital processing system comprising:

an encryption/decryption circuit comprising a random number generator having,

a latch having a data input and a clock input;

20. The digital processing system of claim 19 wherein the programmable bit source further includes a programmable voltage source coupled to a bias input of the latch.

21. The digital processing system of claim 20 wherein the latch has an adjustable trip point, wherein the adjustable trip of the latch is alterable by a voltage output by the programmable voltage source.

22. The digital processing system of claim 20 wherein the encryption/decryption circuit to encode and decode messages transmittal and received by the digital processing system using a cipher-based cryptographic method.

24. The digital processing system of claim 22 wherein the cipher-based cryptographic method is a public key/private key system.

23. The digital processing system of clai 22 wherein the cipher-based crytpgraphic method is a single key system.

26. A random bit source comprising:

a latch to produce a uniform duty cycle output;

a component to test the duty cycle; and

a programmable voltage source to vary an output voltage if the duty cycle has not substantially reached a first threshold and iteratively alter the output voltage until the duty cycle has not substantially reached the first threshold.

27. The random bit source of claim 26 further comprising:

a high frequency oscillator to generate a high frequency signal; and

a low frequency oscillator to generate a low frequency signal;

wherein the latch periodically latches the high frequency signal in response to a low frequency signal and transmits one or more binary digits corresponding to a voltage level of the high frequency signal.

28. The random bit source of claim 26 wherein the programmable voltage source comprises a flash memory cell, wherein varying the output voltage of the voltage circuit further comprises updating a threshold voltage of the flash memory cell.

29. The random bit source of claim 26 wherein the programmable voltage source further comprises differential amplifier, wherein varying the output voltage of the programmable voltage source further comprises varying an input current to a non-inverting input of the differential amplifier to produce a first input voltage and varying an input current to an inverting input of the differential amplifier to produce a second input voltage.

30. The random bit source of claim 26 wherein varying the output voltage of the programmable voltage source further comprises altering the number of transistors in the programmable voltage source determining the output voltage.

31. The random bit source of claim 26 wherein producing a uniform duty cycle output from the random bit source is used in a random number generator operable to produce random binary numbers for use in a cryptographic system for secure communications between a plurality of computers in a network.

32. The random bit source of claim 26 wherein the first threshold is fifty percent