Advanced processor with mechanism for packet distribution at high line rate
First Claim
1. An advanced processor, comprising:
- a packet distribution engine (PDE) configured to receive a plurality of packets from a networking input and to provide the plurality of packets in a substantially load-balanced distribution to a selected group of multiple threads; and
a plurality of processor cores configured to execute the multiple threads.
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Abstract
An advanced processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and configured to pass information among the processor cores. A messaging network is coupled to each of the processor cores and a plurality of communication ports. In one aspect of an embodiment of the invention, the data switch interconnect is coupled to each of the processor cores by its respective data cache, and the messaging network is coupled to each of the processor cores by its respective message station. Advantages of the invention include the ability to provide high bandwidth communications between computer systems and memory in an efficient and cost-effective manner.
164 Citations
31 Claims
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1. An advanced processor, comprising:
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a packet distribution engine (PDE) configured to receive a plurality of packets from a networking input and to provide the plurality of packets in a substantially load-balanced distribution to a selected group of multiple threads; and
a plurality of processor cores configured to execute the multiple threads. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A method of controlling a flow of packets, the method comprising the steps of:
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(a) receiving a plurality of packets from a networking input;
(b) placing the plurality of packets in a packet distribution engine (PDE);
(c) determining a selected group of multiple threads, the multiple threads being executable by a plurality of processor cores; and
(d) providing the plurality of packets from the PDE in a substantially load-balanced distribution to the selected group of multiple threads. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22)
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23. An advanced processing system, comprising:
a plurality of processor cores configured to execute multiple threads and to process a plurality of packets, the plurality of packets being received by a networking input, the plurality of packets being provided to the plurality of processor cores by a packet distribution engine (PDE), the plurality of packets being further provided in a substantially load-balanced distribution to a selected group of the multiple threads. - View Dependent Claims (24, 25, 26, 27, 28, 29, 30, 31)
Specification