System and method for DMA transfer of data in scatter/gather mode
First Claim
1. A method of transferring data between a processor and an attached direct memory access (“
- DMA”
) device in scatter/gather mode comprising;
a) maintaining a table of buffer descriptors for determining a start address and size of a next buffer to be used when transferring data when a current buffer counter reaches zero, wherein entries in the table are linked programmatically;
b) transferring data between a current buffer and the device via DMA;
c) automatically switching buffers when the selected buffer counter reaches zero, wherein a next buffer descriptor table entry is read from memory and a new buffer pointer and size is updated based on the table entry; and
d) transferring data between the next buffer and the device via DMA.
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Accused Products
Abstract
A method and system for DMA transfer of data in scatter/gather mode. A table of buffer descriptors may be used to determine the next buffer to be used when a current buffer storing data that has been transferred or will be transferred and may be used in automatic buffer switching, which does not require processor intervention. Entries in the table of buffer descriptors are entered programmatically. The method and system also provide for hardware writing to table of packet descriptors which describes location and size of incoming data and can indicate whether a packet of data straddles two or more buffers, thus decoupling packet sizes from buffer sizes.
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Citations
32 Claims
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1. A method of transferring data between a processor and an attached direct memory access (“
- DMA”
) device in scatter/gather mode comprising;
a) maintaining a table of buffer descriptors for determining a start address and size of a next buffer to be used when transferring data when a current buffer counter reaches zero, wherein entries in the table are linked programmatically;
b) transferring data between a current buffer and the device via DMA;
c) automatically switching buffers when the selected buffer counter reaches zero, wherein a next buffer descriptor table entry is read from memory and a new buffer pointer and size is updated based on the table entry; and
d) transferring data between the next buffer and the device via DMA. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
- DMA”
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13. A processor configured to transfer data between the processor and an attached direct memory access (“
- DMA”
) device in scatter/gather mode comprising;
a) means for connecting the processor to a DMA device;
b) a plurality of buffers for storing data transferred between the DMA device and the processor, each of the plurality of buffers having a buffer counter;
c) a buffer descriptor table for each Data In FIFO and each Data Out FIFO of a DMA channel transferring data between the DMA device and the processor, each entry in the buffer descriptor table having a buffer address of one of the plurality of buffers, a buffer size of one of the plurality of buffers, and sequencing information for calculating a start address and size of a next buffer to be used for storing data transferred between the DMA device and the processor when a current buffer counter reaches zero, wherein entries in the buffer descriptor table are made programmatically; and
d) a bus interface unit for transferring data between the DMA device and the processor, the bus interface unit including hardware for automatically fetching the calculated start address and size of the next buffer to be used to store data transferred between the DMA device and the processor from the buffer descriptor table so the bus interface unit can automatically switch buffers for storing data transferred between the DMA device and the processor when the current buffer counter reaches zero. - View Dependent Claims (14, 15, 16, 17, 18)
- DMA”
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19. A method of transferring data between a processor and an attached direct memory access (“
- DMA”
) device in scatter/gather mode comprising;
a) transferring a packet of data from the DMA device to the processor;
b) detecting an end-of-packet condition; and
c) writing out a packet descriptor to a table in memory, wherein the packet descriptor includes a packet start address, a packet size, and a bit indicating whether the packet is split across a buffer boundary. - View Dependent Claims (20, 21, 22, 23, 24, 25, 26, 27)
- DMA”
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28. A processor configured to transfer data between the processor and an attached direct memory access (“
- DMA”
) device in scatter/gather mode comprising;
a) means for connecting the processor to a DMA device;
b) a plurality of buffers for storing data transferred between the DMA device and the processor; and
c) a bus interface unit for transferring data between the DMA device and the processor, the bus interface unit including hardware for detecting an end-of-packet event and writing a packet descriptor to a packet descriptor table for each Data In FIFO of a DMA channel, each packet descriptor having a packet start address, a packet size, and a bit indicating whether the packet is split across a buffer boundary, wherein packet descriptors are written to the packet descriptor table each time an end-of-packet event is detected. - View Dependent Claims (29, 30, 31, 32)
- DMA”
Specification