System and method for DMA transfer of data in scatter/gather mode

• US 20050027901A1
• Filed: 07/26/2004
• Published: 02/03/2005
• Est. Priority Date: 07/31/2003
• Status: Active Grant

• Current Assignee: Cradle IP LLC
• Original Assignee: Cradle Technologies
• Inventors: Longley, Mark, Machnicki, Erik P., Simon, Moshe B.
• Granted Patent: US 7,249,202 B2
• Time in Patent Office: Days
• US Class Current: 710/22
• CPC Class Codes: G06F 2207/382 Reconfigurable for different fixed word lengths multigauge devices G06F2207/3828
• CPC Class Codes: G06F 2207/3828 Multigauge devices, i.e. capable of handling packed numbers without unpacking them
• CPC Class Codes: G06F 7/49921 Saturation, i.e. clipping the result to a minimum or maximum value
• CPC Class Codes: G06F 7/49994 Sign extension
• CPC Class Codes: G06F 7/505 in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination
• CPC Class Codes: G06F 7/523 Multiplying only
• CPC Class Codes: G06F 7/5443 Sum of products for applications thereof, see the relevant places, e.g. G06F17/10, H03H17/00
• CPC Class Codes: G06F 9/3001 Arithmetic instructions
• CPC Class Codes: G06F 9/30036 Instructions to perform operations on packed data, e.g. vector, tile or matrix operations

Abstract

A method and system for DMA transfer of data in scatter/gather mode. A table of buffer descriptors may be used to determine the next buffer to be used when a current buffer storing data that has been transferred or will be transferred and may be used in automatic buffer switching, which does not require processor intervention. Entries in the table of buffer descriptors are entered programmatically. The method and system also provide for hardware writing to table of packet descriptors which describes location and size of incoming data and can indicate whether a packet of data straddles two or more buffers, thus decoupling packet sizes from buffer sizes.

Claims

1. A method of transferring data between a processor and an attached direct memory access (“

DMA”

) device in scatter/gather mode comprising;

a) maintaining a table of buffer descriptors for determining a start address and size of a next buffer to be used when transferring data when a current buffer counter reaches zero, wherein entries in the table are linked programmatically;

b) transferring data between a current buffer and the device via DMA;

c) automatically switching buffers when the selected buffer counter reaches zero, wherein a next buffer descriptor table entry is read from memory and a new buffer pointer and size is updated based on the table entry; and

d) transferring data between the next buffer and the device via DMA.

2. The method of claim 1 further comprising creating a table of packet descriptors for each incoming DMA channel.

3. The method of claim 2 wherein buffer switching further includes updating a buffer pointer and size of the next buffer based on the table entry.

4. The method of claim 1 further comprising boundary aligning input data.

5. The method of claim 1 further comprising generating an end-of-packet interrupt.

6. The method of claim 5 further comprising causing an m-bit write to an address specified in a register, wherein m is a number of bits representing a DMA block transfer size.

7. The method of claim 2 further comprising generating a packet descriptor for the table.

8. The method of claim 6 further comprising throttling packet descriptors when the table is full.

9. The method of claim 1 further comprising generating a buffer end interrupt.

10. The method of claim 9 further comprising causing an m-bit write to an address specified in a register, wherein m is a number of bits representing a DMA block transfer size.

11. The method of claim 1 further comprising appending a status byte to the end of a packet.

12. The method of claim 1 further comprising terminating scatter/gather operation after detecting an end-of-buffer condition when a data stream is finished.

13. A processor configured to transfer data between the processor and an attached direct memory access (“

DMA”

) device in scatter/gather mode comprising;

a) means for connecting the processor to a DMA device;

b) a plurality of buffers for storing data transferred between the DMA device and the processor, each of the plurality of buffers having a buffer counter;

c) a buffer descriptor table for each Data In FIFO and each Data Out FIFO of a DMA channel transferring data between the DMA device and the processor, each entry in the buffer descriptor table having a buffer address of one of the plurality of buffers, a buffer size of one of the plurality of buffers, and sequencing information for calculating a start address and size of a next buffer to be used for storing data transferred between the DMA device and the processor when a current buffer counter reaches zero, wherein entries in the buffer descriptor table are made programmatically; and

d) a bus interface unit for transferring data between the DMA device and the processor, the bus interface unit including hardware for automatically fetching the calculated start address and size of the next buffer to be used to store data transferred between the DMA device and the processor from the buffer descriptor table so the bus interface unit can automatically switch buffers for storing data transferred between the DMA device and the processor when the current buffer counter reaches zero.

14. The processor of claim 13 further comprising the bus interface unit including hardware for detecting an end-of-packet condition.

15. The processor of claim 14 further comprising the bus interface unit including hardware for writing a packet descriptor to a packet descriptor table stored in memory of the processor for each Data In FIFO of the DMA channel transferring data between the DMA device and the processor, each entry in the packet descriptor table having a packet start address, a packet size, and a bit indicating whether the packet is split across a buffer boundary, wherein the packet is descriptor is written after detection of an end-of-packet condition.

16. The processor of claim 14 further comprising the bus interface unit including hardware for boundary aligning input data.

17. The processor of claim 13 further comprising the bus interface unit including hardware for detecting an end-of-buffer condition.

18. The processor of claim 17 further comprising the bus interface unit including hardware for terminating scatter/gather operation after detecting an end-of-buffer condition when a data stream is finished.

19. A method of transferring data between a processor and an attached direct memory access (“

DMA”

) device in scatter/gather mode comprising;

a) transferring a packet of data from the DMA device to the processor;

b) detecting an end-of-packet condition; and

c) writing out a packet descriptor to a table in memory, wherein the packet descriptor includes a packet start address, a packet size, and a bit indicating whether the packet is split across a buffer boundary.

20. The method of claim 19 further comprising resetting a packet size counter.

21. The method of claim 19 further comprising generating an end-of-packet interrupt.

22. The method of claim 21 further comprising initiating packet processing.

23. The method of claim 19 further comprising boundary-aligning input data.

24. The method of claim 19 further comprising throttling packet descriptors when the table is full.

25. The method of claim 19 further comprising maintaining a table of buffer descriptors for determining a start address and size of a next buffer to be used when transferring data when a current buffer counter reaches zero, wherein entries in the table are linked programmatically.

26. The method of claim 25 further comprising automatically switching buffers when the selected buffer counter reaches zero, wherein a next buffer descriptor table entry is read from memory and a new buffer pointer and size is updated based on the table entry.

27. The method of claim 19 further comprising terminating scatter/gather operation after detecting a end-of-buffer condition when a data stream is finished.

28. A processor configured to transfer data between the processor and an attached direct memory access (“

DMA”

) device in scatter/gather mode comprising;

a) means for connecting the processor to a DMA device;

b) a plurality of buffers for storing data transferred between the DMA device and the processor; and

c) a bus interface unit for transferring data between the DMA device and the processor, the bus interface unit including hardware for detecting an end-of-packet event and writing a packet descriptor to a packet descriptor table for each Data In FIFO of a DMA channel, each packet descriptor having a packet start address, a packet size, and a bit indicating whether the packet is split across a buffer boundary, wherein packet descriptors are written to the packet descriptor table each time an end-of-packet event is detected.

29. The processor of claim 28 further comprising the bus interface unit including hardware for boundary aligning input data.

30. The processor of claim 28 further comprising a buffer descriptor table for each Data In FIFO and each Data Out FIFO of a DMA channel transferring data between the DMA device and the processor, each entry in the, buffer descriptor table having a buffer address of one of the plurality of buffers, a buffer size of one of the plurality of buffers, and sequencing information for calculating a start address and size of a next buffer to be used for storing data transferred between the DMA device and the processor when a current buffer counter reaches zero, wherein entries in the buffer descriptor table are made programmatically.

31. The processor of claim 28 further comprising the bus interface unit including hardware for detecting an end-of-buffer condition.

32. The processor of claim 31 further comprising the bus interface unit including hardware for terminating scatter/gather operation after detecting an end-of-buffer condition when a data stream is finished.