System on a chip for networking

• US 20050027911A1
• Filed: 07/02/2004
• Published: 02/03/2005
• Est. Priority Date: 05/18/2001
• Status: Active Grant

• Current Assignee: James Y. Cho, Joseph B. Rowlands, Mark D. Hayter
• Original Assignee: James Y. Cho, Joseph B. Rowlands, Mark D. Hayter
• Inventors: Hayter, Mark D., Rowlands, Joseph B., Cho, James Y.
• Granted Patent: US 7,418,534 B2
• Time in Patent Office: Days
• US Class Current: 710/62
• CPC Class Codes: G06F 13/387 for adaptation of different data processing systems to different peripheral devices, e.g. protocol converters for incompatible systems, open system

Abstract

A system on a chip for network devices. In one implementation, the system on a chip may include (integrated onto a single integrated circuit), a processor and one or more I/O devices for networking applications. For example, the I/O devices may include one or more network interface circuits for coupling to a network interface. In one embodiment, coherency may be enforced within the boundaries of the system on a chip but not enforced outside of the boundaries.

Claims

1. In a networking device, an integrated circuit comprising:

at least one processor; and

one or more network interface circuits configured to communicate on one or more network interfaces;

wherein the processor and the network interfaces are integrated on the integrated circuit.

2. The integrated circuit as recited in claim 1 further comprising a memory controller integrated onto the integrated circuit, the memory controller for coupling to a memory, wherein the one or more network interface circuits are configured to transmit data received from the one or more network interfaces for storage in the memory.

3. The integrated circuit as recited in claim 2 further comprising a cache integrated one the integrated circuit, the cache configured to store one or more cache blocks of data from the memory.

4. The integrated circuit as recited in claim 3 wherein the processor, the cache, and the memory controller are coupled to an interconnect.

5. The integrated circuit as recited in claim 4 further comprising a bridge circuit coupled to the interconnect and to the one or more network interface circuits, wherein the bridge circuit is configured to initiate transactions on the interconnect to transmit data received by the one or more network interfaces to the memory controller.

6. The integrated circuit as recited in claim 1 wherein the one or more network interface circuits comprise at least three network interface circuits coupled to separate network interfaces.

7-19. -19. (Canceled)