SDRAM memory device with an embedded NAND flash controller

• US 20050027928A1
• Filed: 11/12/2003
• Published: 02/03/2005
• Est. Priority Date: 07/31/2003
• Status: Active Grant

• Current Assignee: Innovative Memory Systems, Inc. (Wi-LAN Inc.)
• Original Assignee: M-Systems Flash Disk Pioneers Ltd. (Western Digital Corporation)
• Inventors: Paz, Ziv, Inbar, Dan, Avraham, Meir
• Granted Patent: US 7,752,380 B2
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: G06F 9/4403 Processor initialisation
• CPC Class Codes: G06F 9/4406 Loading of operating system
• CPC Class Codes: G06F 9/44573 Execute-in-place [XIP]
• CPC Class Codes: G11C 14/00 Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down
• CPC Class Codes: G11C 14/0018 whereby the nonvolatile element is an EEPROM element, e.g. a floating gate or metal-nitride-oxide-silicon [MNOS] transistor

Abstract

A memory device includes two dies. A first memory is fabricated on one die. A controller of the first memory is fabricated on the other die. Also fabricated on the other die is another component, such as a second memory, that communicates with a host system using a plurality of signals different from the signals used by the first memory. The device includes a single interface for communicating with the host system using only the respective signals of the second component. In a most preferred embodiment, the first memory is a NAND flash memory and the second memory is a SDRAM.

Claims

1. A memory device comprising:

(a) a first die on which is fabricated a first memory; and

(b) a second die on which are fabricated;

(i) a controller for said first memory, and

(ii) at least one additional component.

2. The memory device of claim 1, wherein said first and second dies are packaged in a common package.

3. The memory device of claim 2, further comprising:

(c) a plurality of pins for operationally connecting said first and second dies to a host system.

4. The memory device of claim 1, wherein said first memory is a nonvolatile memory.

5. The memory device of claim 4, wherein said nonvolatile memory is a flash memory.

6. The memory device of claim 5, wherein said flash memory is a NAND flash memory.

7. The memory device of claim 1, wherein said at least one additional component includes a second memory.

8. The memory device of claim 7, wherein said second memory is a volatile memory.

9. The memory device of claim 8, wherein said volatile memory is a SDRAM.

10. The memory device of claim 9, wherein said controller includes an interface, to a host system, appropriate to said SDRAM.

11. The memory device of claim 9, further comprising:

(c) a single interface to a host system, said interface being appropriate to said SDRAM.

12. The memory device of claim 1, wherein said first memory and said at least one additional component communicate with a host system using different respective pluralities of signals.

13. The memory device of claim 12, wherein said controller includes an interface for communicating with said host system only using said respective signals of said at least one additional component.

14. The memory device of claim 12, further comprising:

(c) a single interface for communicating with said host system only using said respective signals of said at least one additional component.

15. The memory device of claim 1, wherein said controller includes a XIP boot block.

16. The memory device of claim 1, wherein said controller is operative to also manage one of said at least one additional component.

17. The memory device of claim 1, wherein said one of said at least one additional component is a second memory, and wherein said controller provides paging for said second memory.

18. The memory device of claim 1, wherein said one of said at least one additional component is a second memory, and wherein said controller provides hardware decompression for said second memory.

19. A system comprising:

(a) the memory device of claim 1;

(b) a CPU; and

(c) a single bus for communication between said CPU and said memory device.

20. The system of claim 19, wherein said communication is via signals appropriate only to at least one of said at least one additional component.

21. A memory device comprising:

(a) a first die on which is fabricated a first memory and a controller for a second memory.

22. The memory device of claim 21, wherein said second memory is a nonvolatile memory.

23. The memory device of claim 22, wherein said nonvolatile memory is a flash memory.

24. The memory device of claim 23, wherein said flash memory is a NAND flash memory.

25. The memory device of claim 21, wherein said first memory is a volatile memory.

26. The memory device of claim 25, wherein said volatile memory is a SDRAM.

27. The memory device of claim 26, wherein said controller includes an interface, to a host system, appropriate to said SDRAM.

28. The memory device of claim 26, further comprising:

(b) a single interface to a host system, said interface being appropriate to said SDRAM.

29. The memory device of claim 21, further comprising:

(b) a second die on which is fabricated said second memory.

30. The memory device of claim 29, wherein said first and second dies are packaged in a common package.

31. The memory device of claim 30, further comprising:

(c) a plurality of pins for operationally connecting said first and second dies to a host system.

32. The memory device of claim 29, wherein said first and second memories communicate with a host system using different respective pluralities of signals.

33. The memory device of claim 32, wherein said controller includes an interface for communicating with said host system only using said respective signals of said first memory.

34. The memory device of claim 33, further comprising:

(c) a single interface for communicating with said host system only using said respective signals of said first memory.

35. The memory device of claim 21, wherein said controller includes a XIP boot block.

36. The memory device of claim 21, wherein said controller is operative to also manage said first memory.

37. The memory device of claim 21, wherein said controller provides paging for said first memory.

38. The memory device of claim 21, wherein said controller provides decompression for said first memory.

39. A system comprising:

(a) the memory device of claim 21;

(b) a CPU; and

(c) a single bus for communication between said CPU and said memory device.

40. The system of claim 39, wherein said communication is via signals appropriate only to said first memory.

41. The system of claim 39, further comprising:

(d) said second memory.