Latency reduction using negative clock edge and read flags

• US 20050027959A1
• Filed: 08/31/2004
• Published: 02/03/2005
• Est. Priority Date: 08/16/2002
• Status: Active Grant

• Current Assignee: Jeff W. Janzen, Paul A. Laberge
• Original Assignee: Jeff W. Janzen, Paul A. Laberge
• Inventors: LaBerge, Paul A., Janzen, Jeff W.
• Granted Patent: US 7,055,012 B2
• Time in Patent Office: Days
• US Class Current: 711/167
• CPC Class Codes: G06F 13/4243 with synchronous protocol

Abstract

A method of selecting CAS latencies in a system. Specifically, a system which includes a plurality of memory devices and a memory controller is provided. Because different memory devices may have different CAS latencies, a system CAS latency is selected wherein the system CAS latency is the fastest common CAS latency of each of the plurality of memory devices. After a read request is delivered to a memory device, the memory controller initiates a transmission flag to the memory device at a time equal to the system CAS latency, indicating that it is safe to transmit the requested data from the memory device to the memory controller. The transmission flags may be used in conjunction with mode registers such that one or both of the transmission flag and the data may be received by or delivered by a corresponding memory device.

Claims

1. A computer system comprising:

a processor; and

a memory system coupled to the processor and comprising;

a plurality of memory devices configured to store data; and

a memory controller configured to send reads to the plurality of memory devices and configured to initiate corresponding transmission flags to the plurality of memory devices at a time subsequent to the sending of the respective reads, the transmission flags indicating that the data corresponding to the reads can be sent from the plurality of memory devices to the memory controller.

2. The computer system, as set forth in claim 1, wherein the memory controller is configured to initiate the respective transmission flags to the respective plurality of memory devices at a time equal to the fastest CAS latency common to each of the plurality of memory devices.

3. The computer system, as set forth in claim 1, wherein each of the plurality of memory devices comprises a dynamic random access memory (DRAM) device.

4. The computer system, as set forth in claim 1, wherein the plurality of memory devices are distributed on a plurality of memory modules.

5. The computer system, as set forth in claim 4, wherein each of the plurality of memory modules comprises a storage device configured to store the CAS latency of each of the plurality of memory devices on a corresponding memory module.

6. The computer system, as set forth in claim 5, wherein the storage device comprises a serial presence detect (SPD) device.

7. The computer system, as set forth in claim 1, wherein each of the plurality of memory devices comprises a mode register configured to allow for receipt of the respective transmission flags on a negative edge of a clock signal.

8. The computer system, as set forth in claim 1, wherein each of the plurality of memory devices comprises a mode register configured to allow for sending the data corresponding to the read to the memory controller on a negative edge of a clock cycle.

9. A computer system comprising:

a processor; and

a memory system comprising a memory controller coupled to a plurality of memory devices, wherein the computer system is configured to;

initiate a read to the memory controller;

send the read from the memory controller to a corresponding one of the plurality of memory devices;

fetch data corresponding to the read;

initiate a transmission flag to the corresponding one of the plurality of memory devices; and

send the data from the one of the plurality of memory devices to the memory controller in response to the transmission flag.

10. The computer system, as set forth in claim 9, wherein the computer system is further configured to:

determine a system CAS latency, the system CAS latency comprising the fastest CAS latency common to each of the plurality of memory devices in the system; and

store the system CAS latency in the memory controller.

11. The computer system, as set forth in claim 10, wherein the computer system is configured to initiate the transmission flag at a time after sending the read to the one of the plurality of memory devices, wherein the time is equal to the system CAS latency.

12. The computer system, as set forth in claim 10, wherein the computer system is configured to read a configuration device associated with the one of the plurality of memory devices to determine the CAS latencies which are achievable by the plurality of memory devices.

13. The computer system, as set forth in claim 12, wherein the computer system is configured to read the configuration device at system initialization.

14. The computer system, as set forth in claim 9, wherein the computer system is further configured to:

capture the transmission flag at the corresponding one of the plurality of memory devices on a first positive edge of a clock signal; and

send the data from the corresponding one of the plurality of memory devices on a second positive edge of the clock signal, the second positive edge being subsequent to the first positive edge of the clock signal.

15. The computer system, as set forth in claim 9, wherein the computer system is further configured to enable the plurality of memory devices to capture the transmission flag on a negative edge of a clock signal using a mode register.

16. The computer system, as set forth in claim 15, wherein the computer system is further configured to:

capture the transmission flag at the corresponding one of the plurality of memory devices on a negative edge of a clock signal; and

send the data from the corresponding one of the plurality of memory device on a positive edge of the clock signal, the positive edge being subsequent to the negative edge of the clock signal.

17. The computer system, as set forth in claim 9, wherein the computer system is configured to enable the one of the plurality of memory devices to send the data on a negative edge of a clock signal using a mode register.

18. The computer system, as set forth in claim 17, wherein the computer system is further configured to:

capture the transmission flag at the corresponding one of the plurality of memory devices on a positive edge of a clock signal; and

send the data from the corresponding one of the plurality of memory devices on a negative edge of the clock signal, the negative edge being subsequent to the positive edge of the clock cycle.

19. The computer system, as set forth in claim 9, wherein the computer system is further configured to:

enable the one of the plurality of memory devices to capture the transmission flag on a first negative edge of a clock signal using a first mode register; and

enable the one of the plurality of memory devices to send the data on a second negative edge of the clock signal using a second mode register.

20. The computer system, as set forth in claim 19, wherein the computer system is further configured to:

capture the transmission flag at the corresponding one of the plurality of memory devices of a first negative edge of a clock cycle; and

send the data from the corresponding one of the plurality of memory devices on a second negative edge of the clock cycle, the second negative edge being subsequent to the first negative edge of the clock cycle.

21. The computer system, as set forth in claim 14, wherein the computer system is configured to capture the transmission flag at the corresponding one of the plurality of memory devices on an edge of a command/address clock.

22. The computer system, as set forth in claim 16, wherein the computer system is configured to capture the transmission flag at the corresponding one of the plurality of memory devices on an edge of a command/address clock.

23. The computer system, as set forth in claim 18, wherein the computer system is configured to capture the transmission flag at the corresponding one of the plurality of memory devices on an edge of a command/address clock.

24. The computer system, as set forth in claim 20, wherein the computer system is configured to capture the transmission flag at the corresponding one of the plurality of memory devices on an edge of a command/address clock.