Defining instruction extensions in a standard programming language

• US 20050027971A1
• Filed: 07/29/2003
• Published: 02/03/2005
• Est. Priority Date: 07/29/2003
• Status: Active Grant

• Current Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Original Assignee: STRETCH, INC (Maxlinear Incorporated)
• Inventors: Williams, Kenneth M., Wang, Albert
• Granted Patent: US 7,373,642 B2
• Time in Patent Office: Days
• US Class Current: 712/227
• CPC Class Codes: G06F 9/30043 LOAD or STORE instructions; Clear instruction
• CPC Class Codes: G06F 9/3816 Instruction alignment, e.g. cache line crossing
• CPC Class Codes: G06F 9/383 Operand prefetching cache prefetching G06F12/0862

Abstract

A method is provided for modifying a program written in a standard programming language so that when the program is compiled both an executable file is produced and an instruction is programmed into a programmable logic device of a processor system. The method includes identifying a critical code segment of a program, rewriting the critical code segment as a function, revising the program, and compiling the program. Revising the program includes designating the function as code to be compiled by an extension compiler and replacing the critical code segment of the program with a statement that calls the function. Compiling the program includes compiling the code with an extension compiler to produce a header file and the instruction for the programmable logic device. Compiling the program also includes using a standard compiler to compile the remainder of the program together with the header file to generate the executable file.

Claims

1. A method for modifying a program to allow the program to execute on a processor system that includes a programmable logic device, the method comprising:

identifying a critical code segment of the program;

rewriting the critical code segment as a function;

revising the program by designating the function as a code to be compiled by an extension compiler and by replacing the critical code segment with a statement that calls the function; and

compiling the revised program such that the function is executed by the programmable logic device.

2. The method of claim 1 wherein the critical code segment is defined by the length of time required for execution.

3. The method of claim 1 wherein the critical code segment is a nested loop.

4. The method of claim 1 wherein the program is written in a programming language and the function is written with the same programming language.

5. The method of claim 1 wherein the function is selected from a library of pre-defined functions.

6. The method of claim 1 wherein the function defines an integer with a non-standard number of bits.

7. The method of claim 1 wherein the program is written in a program file and designating the function as a code includes writing the code to an extensions file.

8. The method of claim 1 wherein compiling the revised program includes copying the code to an extensions file.

9. The method of claim 1 wherein compiling the revised program includes compiling an extensions file including the code to produce a header file and an intermediate file written in a hardware description language.

10. The method of claim 1 wherein the step of revising is performed manually.

11. The method of claim 1 wherein the step of revising is performed using an automated conversion tool.

12. The method of claim 9 wherein the hardware description language is Verilog HDL.

13. The method of claim 9 wherein the header file declares a prototype for the function.

14. The method of claim 9 wherein the intermediate file includes an implementation of the function as an instruction for a programmable logic device.

15. The method of claim 10 wherein the header file and the revised program are compiled together by a standard compiler to generate an executable file.

16. The method of claim 15 wherein the standard compiler also includes the compiling of a configuration file in generating the executable file.

17. The method of claim 1 further comprising:

profiling the revised program; and

evaluating the performance of the revised program.

18. The method of claim 17 wherein evaluating the performance of the revised program includes comparing the performance against a timing requirement.

19. The method of claim 17 wherein evaluating the performance of the revised program includes comparing the performance against a prior performance.

20. The method of claim 1 wherein the function executed by the programmable logic device does not have direct access to non-register file memory.

21. The method of claim 1 wherein the function executed by the programmable logic device has register file inputs and outputs limited to a predetermined number set by the compiler.

22. The method of claim 21 wherein the limited predetermined number of register file inputs is three.

23. A computer-readable medium comprising program instructions, the program instructions comprising:

computer code to be compiled by an extension compiler to generate a header file and an intermediate file for programming a programmable logic device coupled to a processor; and

computer code to be compiled together with the header file by a standard compiler to generate an executable file.

24. The computer-readable medium comprising program instructions of claim 23, wherein the computer code to be compiled by the extension compiler is separated by flags from the computer code to be compiled by the standard compiler.

25. The computer-readable medium comprising program instructions of claim 24, wherein the computer code to be compiled by the standard compiler is contained in a program file, and computer code to be compiled by the extension compiler is contained in an extensions file.

26. The computer-readable medium comprising program instructions of claim 23, wherein the standard compiler is a C++ compiler.

27. A computer system for executing a program including both standard code and extension code, comprising:

a processing system including a processor core and a programmable logic device;

an extension compiler for compiling the extension code to produce a header file and an intermediate file that specifies an instruction for the programmable logic device; and

a standard compiler for compiling the standard code together with the header file to produce an executable file.

28. The computer system of claim 27, wherein at least one of the header file and the intermediate file is written in Verilog HDL.

29. The computer system of claim 27, further comprising an implementation tool for converting the intermediate file into a PLD configuration file.

30. The computer system of claim 27, wherein the header file is adapted to declare a function used to execute an extended instruction called out by the extension compiler during compilation of the extension code.

31. The computer system of claim 30, wherein the function is selected from a library of pre-selected functions.

32. The computer system of claim 30, wherein the function defines an integer with a non-standard number of bits.

33. The computer system of claim 30, wherein the function is a prototype.

34. The computer system of claim 30, wherein the standard compiler is a C++ compiler.

35. The computer system of claim 30, wherein inputs and outputs to the programmable logic device are limited to data transfers with a register file.

36. The computer system of claim 35, wherein the number of register file inputs are limited to a predetermined number set by the compiler.

37. The computer system of claim 36, wherein the limited predetermined number of register file inputs is three.

38. A method for extending the native instruction set of a general purpose processor in a computing system comprising a general purpose processor and a programmable logic device, the method consisting of the steps of:

(i) identifying critical code segments in an application program to be run on the computing system;

(ii) replacing the critical code segments with at least one extended instruction, not included in the native instruction set of the processor;

(iii) compiling the application program including the code segments containing the extended instruction; and

(iv) executing the compiled application program on the computer system such that the native instructions are executed by the processor and the extended instruction is executed by the programmable logic device.

39. The method of claim 38 wherein the critical code segment is defined by the length of time required for execution.

40. The method of claim 38 wherein the critical code segment is a nested loop.

41. The method of claim 38 wherein the at least one extended instruction is selected from a library of predefined extended instructions.

42. The method of claim 38 wherein compiling the application program includes copying the application program to an extensions file.

43. The method of claim 38 wherein compiling the application program includes compiling an extensions file including the code to produce a header file and an intermediate file written in a hardware description language.

44. The method of claim 43 wherein the hardware description language is Verilog HDL.

45. The method of claim 38 wherein the step of revising is performed manually.

46. The method of claim 38 wherein the step of revising is performed using an automated conversion tool.

47. A compiler for extending the native instruction set of a general purpose processor in a computing system comprising a general purpose processor and a programmable logic device, the compiler comprising:

an input for receiving uncompiled object code of an application program;

a header file output coupled to the input for generating compiled programming code for execution by the computer system; and

an intermediate file output for generating instructions for configuring the programmable logic device to execute extended instructions.

48. The compiler of claim 47 wherein the compiler generates outputs in C.

49. The compiler of claim 47 wherein the compiler allocates register files.

50. The compiler of claim 47, wherein the header file output declares a function used to execute an extended instruction.

51. The compiler of claim 50, wherein the function is selected from a library of pre-selected functions.

52. The compiler of claim 50, wherein the function defines an integer with a non-standard number of bits.

53. The compiler of claim 50, wherein the function is a prototype.

54. A system for modifying a program to allow the program to execute on a processor system that includes a programmable logic device, comprising:

means for identifying a critical code segment of the program;

means for rewriting the critical code segment as a function;

means for revising the program by designating the function as a code to be compiled by an extension compiler and by replacing the critical code segment with a statement that calls the function; and

means for compiling the revised program such that the function is executed by the programmable logic device.

55. The system of claim 54 wherein the critical code segment is defined by the length of time required for execution.

56. The system of claim 54 wherein the critical code segment is a nested loop.

57. The system of claim 54 wherein the program is written in a programming language and the function is written with the same programming language.

58. The system of claim 54 wherein the function is selected from a library of pre-defined functions.

59. The system of claim 54 wherein the function defines an integer with a non-standard number of bits.

60. The system of claim 54 wherein the program is written in a program file and means for revising the program by designating the function as a code includes means for writing the code to an extensions file.

61. The system of claim 54 wherein the program is written in a program file and means for revising the program by designating the function as a code includes means for writing the code into the program file and demarking the code.

62. The system of claim 54 wherein means for compiling the revised program includes means for copying the code to an extensions file.

63. The system of claim 54 wherein means for compiling the revised program includes means for compiling an extensions file including the code to produce a header file and an intermediate file written in a hardware description language.

64. The system of claim 63 wherein the hardware description language is Verilog HDL.

65. The system of claim 63 wherein the header file declares a prototype for the function.

66. The system of claim 63 wherein the intermediate file includes an implementation of the function as an instruction for a programmable logic device.

67. The system of claim 63 wherein the header file and the revised program are compiled together by a standard compiler to generate an executable file.

68. The system of claim 54 further comprising:

means for profiling the revised program; and

means for evaluating the performance of the revised program.

69. The system of claim 68 wherein the means for evaluating the performance of the revised program includes means for comparing the performance against a timing requirement.

70. The system of claim 68 wherein the means for evaluating the performance of the revised program includes means for comparing the performance against a prior performance.

71. The system of claim 54 wherein the function executed by the programmable logic device does not have direct access to non-register file memory.

72. The system of claim 54 wherein the function executed by the programmable logic device has register file inputs and outputs limited to a predetermined number set by the compiler.

73. The system of claim 54 wherein the limited predetermined number of register file inputs is three.

74. A method for modifying a program to allow the program to execute on a processor system that includes a programmable logic device, the method comprising:

identifying a critical code segment of the program;

demarking the critical code segment;

revising the program by designating the demarked code segment as a code to be compiled by an extension compiler and by replacing the critical code segment with one or more extended instructions; and

compiling the revised program such that the extended instructions are executed by the programmable logic device.