Memory arrangement in a computer system

• US 20050028040A1
• Filed: 07/30/2004
• Published: 02/03/2005
• Est. Priority Date: 07/31/2003
• Status: Active Grant

• Current Assignee: Polaris Innovations Limited (Wi-LAN Inc.)
• Original Assignee: Qimonda AG (Infineon Technologies AG)
• Inventors: Perner, Martin
• Granted Patent: US 7,313,732 B2
• Time in Patent Office: Days
• US Class Current: 714/42
• CPC Class Codes: G06F 11/2294 by remote test

Abstract

A memory arrangement in a computer system can have at least one memory module with semiconductor components, which are arranged on the memory module, can be operated in parallel and are additionally connected to one another via a serial line. The memory arrangement can have an interface bus for driving the semiconductor components on a module-specific basis, and an interface, which is driven by a memory controller assigned to the memory module via the interface bus and accesses the semiconductor components via the serial line. During normal operation, it is possible to test and adjust the semiconductor components in proximity to the application and on a chip-specific basis via the interface.

Claims

1. A memory arrangement in a computer system, comprising:

at least one memory module with semiconductor components, the semiconductor components being arranged on the memory module, operating in parallel, and being connected to one another via a serial line;

an interface bus for driving the semiconductor components on a module-specific basis; and

an interface driven by a memory controller, assigned to the memory module via the interface bus, and accesses the semiconductor components via the serial line, wherein, during normal operation, the interface tests and adjusts the semiconductor components in proximity to the application and on a chip-specific basis.

2. The memory arrangement according to claim 1, further comprising:

a test system connected to the computer system via a remote connection to test and adjust the semiconductor components via the interface.

3. The memory arrangement according to claim 2, wherein the remote connection is a LAN or WAN connection.

4. The memory arrangement according to claim 1, wherein the interface has a circuit arrangement, the circuit arrangement designed such that an input code applied to the interface is converted into serial signals which are passed via the serial line through the semiconductor components connected to the serial line and a result signal is received.

5. The memory arrangement according to claim 4, wherein the serial signals initiate parameter requesting, configuration, and/or adjustment of an operating mode of the semiconductor components in order to ascertain and output the result signals.

6. The memory arrangement according to claim 4, wherein the circuit arrangement is an ASIC.

7. The memory arrangement according to claim 4, wherein the circuit arrangement stores the result signals which have been ascertained and/or forwards them to the memory controller.

8. The memory arrangement according to claim 4, wherein each semiconductor component has an associated flexibly programmable test unit, the test unit, on the basis of the serial signals supplied to the semiconductor component via the serial connection, transmiting test modes for ascertaining test data on the semiconductor component, processing the test data, using the test data for further boot and/or test operations during normal operation in order to adjust the semiconductor component in proximity to the application, and forwarding the test data as result signals to the interface for output.

9. The memory arrangement according to claim 4, wherein the test unit in the semiconductor components can be programmed via the interface.

10. The memory arrangement according to claim 1, further comprising:

at least one further memory module with semiconductor components, the semiconductor components being arranged on the further memory module, operated in parallel and connected to one another via a serial line, the semiconductor components on the memory module and the semiconductor components on the at least one further memory module being driven in parallel via the serial lines.

11. The memory arrangement according to claim 1, further comprising:

at least one further memory module, the serial line connecting the semiconductor components in the memory module, the serial line being looped through the at least one further memory module such that the semiconductor components on the memory module and on the at least one further memory module are connected to one another in series.

12. The memory arrangement according to claim 1, wherein the interface is integrated in the memory controller and the memory controller is connected directly to the serial line that connects the semiconductor components on the memory module.

13. The memory arrangement according to claim 1, wherein the interface is formed by an interface card supported by the memory controller.

14. The memory arrangment of claim 9, wherein the test unit is programmed with firmware or function tests.