Semiconductor device and a method of manufacturing the same

• US 20050029584A1
• Filed: 07/08/2004
• Published: 02/10/2005
• Est. Priority Date: 08/04/2003
• Status: Abandoned Application

• Current Assignee: Renesas Technology Corporation (Renesas Electronics Corporation)
• Original Assignee: Renesas Technology Corporation (Renesas Electronics Corporation)
• Inventors: Shiraishi, Masaki, Nakazawa, Yoshito
• Application Number:
  US10/886,041
• Publication Number:
  US 20050029584A1
• Time in Patent Office: Days
• US Class Current: 257/329
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 2224/05552 in top view
• CPC Class Codes: H01L 2224/0603 Bonding areas having different sizes, e.g. different heights or widths
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/4925 with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with only a vertical doping structure or vertical doping variation H01L29/4916
• CPC Class Codes: H01L 29/4933 with a silicide layer contacting the silicon layer, e.g. Polycide gate with a barrier layer between the silicide and silicon layers H01L29/4941
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/1305 Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/1306 Field-effect transistor [FET]
• CPC Class Codes: H01L 2924/13062 Junction field-effect transistor [JFET]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]

Abstract

A technology is provided to reduce ON-resistance, and the prevention of punch through is achieved with respect to a trench gate type power MISFET. Input capacitance and a feedback capacitance are reduced by forming a groove in which a gate electrode is formed so as to have a depth as shallow as about 1 μm or less, a p⁻type semiconductor region is formed to a depth so as not to cover the bottom of the groove, and a p-type semiconductor region higher in impurity concentration than the p⁻type semiconductor region is formed under a n⁺type semiconductor region serving as a source region of the trench gate type power MISFET, causing the p-type semiconductor region to serve as a punch-through stopper layer of the trench gate type power MISFET.

Claims

1. A semiconductor device including a plurality of MISFETs, comprising:

a first semiconductor layer having a first conductivity type, formed over a first surface of a semiconductor substrate;

a second semiconductor layer having a second conductivity type opposite to the said first conductivity type, formed over said first semiconductor layer;

a plurality of first groove parts equal to or less than 1 μ

m in depth, formed in said first surface of said semiconductor substrate, wherein at least a portion of said first groove parts are in contact with said first semiconductor layer;

a first insulating film formed over the sidewall and bottom of each of said first groove parts;

a first conductor formed over said first insulating film, wherein said first conductor fills at least a portion of each of said first groove parts;

a third semiconductor layer formed in said second semiconductor layer having said first conductivity type, wherein said third semiconductor layer is adjacent to each of said first groove parts;

a fourth semiconductor layer having said second conductivity type, formed in the second semiconductor layer between the first groove parts adjacent to each other; and

a first electrode electrically connected to said third semiconductor layer and said fourth semiconductor layer;

wherein said first semiconductor layer and said third semiconductor layer form one selected from the group consisting of a source and drain of each of said plurality of MISFETs, and wherein said second semiconductor layer forms a channel forming region of each of said plurality of MISFETs; and

wherein a fifth semiconductor layer having said second conductivity type and a higher impurity concentration than said second semiconductor layer, is formed in said second semiconductor layer.

2. A semiconductor device according to claim 1, wherein said fifth semiconductor layer forms a punch-through stopper layer.

3. A semiconductor device according to claim 1, further comprising a second electrode electrically connected to said first conductor, formed of a second conductor lower in resistivity than said first conductor.

4. A semiconductor device according to claim 3,

wherein said plurality of MISFETs are formed in at least one chip region of said semiconductor substrate, and

wherein said second electrode has a first part formed along the periphery of said at least one chip region and a second part extended in said at least one chip region on at least a portion of the inner side of said first part.

5. A semiconductor device according to claim 1, wherein said first groove parts each have a depth equal to or less than 1.1 times a depth of said second semiconductor layer.

6. A semiconductor device according to claim 5, wherein the magnitude of a portion of each of said first groove parts, extending from said second semiconductor layer, is less than or about 0.1 μ

m.

7. A semiconductor device according to claim 1 wherein a sixth semiconductor layer having said first conductivity type is formed under said first groove parts.

9. semiconductor device according to claim 1,

wherein a second groove part penetrating from said first surface of said semiconductor substrate through said third semiconductor layer is formed between said first groove parts adjacent to each other,

wherein said fourth semiconductor layer is formed to cover at a portion of said second groove parts, and

wherein said first electrode is formed to fill at least a portion of said second groove parts.

10. A semiconductor device according to claim 1, wherein each of said plurality of MISFETs is for use as a switching element of a DC-DC converter.

11. A semiconductor device including a plurality of MISFETs, comprising:

a first semiconductor layer having a first conductivity type, formed over a first surface of a semiconductor substrate;

a second semiconductor layer having a second conductivity type opposite to said first conductivity type, formed over said first semiconductor layer;

a plurality of first groove parts having a depth less than or equal to 1 μ

m, and less than or equal to 1.1 times a depth of said second semiconductor layer, formed in said first surface of said semiconductor substrate, wherein at least a lower portion of the said first groove parts is in contact with said first semiconductor layer;

a first insulating film formed over at least a portion of a sidewall and bottom of each of said first groove parts;

a first conductor formed over said first insulating film, filling up at least a portion of said first groove parts;

a third semiconductor layer having said first conductivity type, formed in said second semiconductor layer adjacent to said first groove parts;

a fourth semiconductor layer having said second conductivity type, formed in said second semiconductor layer between adjacent ones of said first groove parts;

a first electrode electrically connected to said third semiconductor layer and said fourth semiconductor layer; and

a second electrode electrically connected to said first conductor, formed of a second conductor lower in resistivity than said first conductor;

wherein said first semiconductor layer and said third semiconductor layer form one selected from the group consisting of a source and a drain of each of said plurality of MISFETs, and said second semiconductor layer forms a channel forming region for each of said plurality of MISFETs;

wherein a fifth semiconductor layer having said second conductivity type and a higher impurity concentration than said second semiconductor layer, is formed in said second semiconductor layer; and

wherein said second electrode has a first part formed along the periphery of at least one chip region and a second part extended in the at least one chip region in at least a portion of the inner side of said first part.

8. A semiconductor device according to claim 11, wherein the threshold voltage of each of said plurality of MISFETs is less than or about 2V.

12. A semiconductor device according to claim 11, wherein said fifth semiconductor layer forms a punch-through stopper layer.

13. A semiconductor device according to claim 11,

wherein a second groove part penetrating from said first surface of said semiconductor substrate through said third semiconductor layer is formed between the first groove parts;

wherein said fourth semiconductor layer is formed to cover at least a portion of the bottoms of said second groove parts, and

wherein said first electrode is formed to fill up at least a portion of said second groove parts.

14. A semiconductor device including a plurality of vertical power MISFETs having trench gate electrodes over a semiconductor substrate, said plurality of vertical power MISFETs each comprising:

a source region formed at the top surface side of said semiconductor substrate;

a drain region formed at the back surface of said semiconductor substrate; and

a channel forming region formed between said source region and said drain region;

wherein a groove for forming said trench gate electrodes is about or less than 1 μ

m in depth; and

wherein a punch-through stopper layer is formed inside said channel forming region.

15. A semiconductor device according to claim 14, wherein said trench gate electrodes are electrically connected to at least one gate finger portion lower in resistivity than said trench gate electrodes.

16. A semiconductor device including a plurality of vertical power MISFETs, comprising:

a semiconductor substrate;

grooves formed in the top surface of said semiconductor substrate extending in a first direction;

a gate insulator formed in said respective grooves;

a gate electrode formed over said gate insulator in the respective grooves;

a source region formed at said top surface side of said semiconductor substrate;

a drain region formed at said back surface side of said semiconductor substrate; and

a channel forming region formed between said source region and the drain region;

wherein a gate capacitance of said gate electrodes is less than or equal to 1×

10<sup>−

3</sup> pF per 1 μ

m in said first direction, wherein a voltage of 0V is applied to said gate electrode and said source region and a voltage of less than 10V is applied to said drain region at a frequency of about 1 MHz; and

wherein a punch-through stopper layer is formed inside said channel forming region.

17. A semiconductor device including a plurality of MISFETs formed in a chip region of a semiconductor substrate, comprising:

a first semiconductor layer having a first conductivity type, formed over the top surface of said semiconductor substrate;

a second semiconductor layer having a second conductivity type opposite to said first conductivity type, formed over said first semiconductor layer;

a plurality of first groove parts less than 1 μ

m in depth, formed in said top surface of said semiconductor substrate, and penetrating from said top surface of said semiconductor substrate through said second semiconductor layer, at least a portion of the bottom thereof being in contact with said first semiconductor layer;

a first insulating film formed over said sidewall and bottom of each of said first groove parts;

a first conductor formed over said first insulating film, wherein said first conductor fills a portion of said first groove parts;

a third semiconductor layer having said first conductivity type, formed in said second semiconductor layer adjacent to said respective first groove parts;

a fourth semiconductor layer having said second conductivity type, formed in said second semiconductor layer between said first groove parts adjacent to each other;

a first electrode electrically connected to said third semiconductor layer and said fourth semiconductor layer; and

a second electrode electrically connected to said first conductor, formed of a second conductor lower in resistivity than said first conductor;

wherein said first semiconductor layer and said third semiconductor layer form one selected form the group consisting of a source and a drain of each of said plurality of MISFETs and the second semiconductor layer forms at least one channel forming region of each of said plurality of MISFETs, and

wherein said second electrode has a first part formed along the periphery of said chip region and a second part extended in said chip region at the inner side of said first part.

18. A semiconductor device including a plurality of MISFETs, comprising:

a first semiconductor layer having a first conductivity type, formed over a first surface of a semiconductor substrate;

a second semiconductor layer having a second conductivity type opposite to said first conductivity type, formed over said first semiconductor layer;

a plurality of first groove parts less than 1 μ

m in depth, formed in the first surface of said semiconductor substrate, wherein at least a portion of the plurality of first groove parts are in contact with said first semiconductor layer;

a first insulating film formed over a side and a bottom of each of said plurality of first groove parts;

a first conductor formed over said first insulating film, wherein said first conductor fills at least one portion of the plurality of the first groove parts;

a third semiconductor layer having said first conductivity type, formed in said second semiconductor layer adjacent to said plurality of first groove parts;

a fourth semiconductor layer having said second conductivity type, formed in said second semiconductor layer between adjacent ones of said plurality of first groove parts; and

a first electrode electrically connected to said third semiconductor layer and said fourth semiconductor layer,

wherein said first semiconductor layer and said third semiconductor layer form one selected from the group consisting of a source and a drain of each of said plurality of MISFETs, said second semiconductor layer forms at least one channel forming region of each of said plurality of MISFETs, and wherein said first conductor is formed of a stacked silicon film and one selected from the group consisting of a silicon compound film and a metal film.

19-21. -21. (Cancelled)

22. A semiconductor device, comprising:

at least one epitaxial layer formed over a first surface of a semiconductor substrate;

at least one transistor trench gate protruding into said epitaxial layer; and

a punch-through stopper layer formed on said epitaxial layer and surrounding said trench gate;

wherein said punch-through stopper layer has a substantially flat impurity profile, and a depth of about 0.1 to about 0.4 μ

m.