Gate dielectric antifuse circuit to protect a high-voltage transistor
First Claim
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1. A method of operating an antifuse circuit comprising:
- coupling an elevated voltage to a first terminal of an antifuse in an antifuse circuit during a programming mode of operation, the antifuse comprising a layer of gate dielectric between the first terminal and a second terminal;
bearing a portion of the elevated voltage on a high-voltage transistor coupled to the second terminal of the antifuse during the programming mode;
coupling a first intermediate voltage between the elevated voltage and a supply voltage to a gate terminal of the high-voltage transistor to protect the high-voltage transistor during the programming mode;
coupling a read voltage to the first terminal of the antifuse during an active mode of operation when the antifuse is being read; and
coupling a second intermediate voltage between the read voltage and the supply voltage to the gate terminal of the high-voltage transistor during the active mode.
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Abstract
According to embodiments of the present invention, circuits have elements to protect a high-voltage transistor in a gate dielectric antifuse circuit. An antifuse has a layer of gate dielectric between a first terminal coupled to receive an elevated voltage and a second terminal, and a high-voltage transistor is coupled to the antifuse and has a gate terminal. An intermediate voltage between the supply voltage and the elevated voltage is coupled to the gate terminal of the high-voltage transistor to protect the high-voltage transistor.
55 Citations
24 Claims
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1. A method of operating an antifuse circuit comprising:
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coupling an elevated voltage to a first terminal of an antifuse in an antifuse circuit during a programming mode of operation, the antifuse comprising a layer of gate dielectric between the first terminal and a second terminal;
bearing a portion of the elevated voltage on a high-voltage transistor coupled to the second terminal of the antifuse during the programming mode;
coupling a first intermediate voltage between the elevated voltage and a supply voltage to a gate terminal of the high-voltage transistor to protect the high-voltage transistor during the programming mode;
coupling a read voltage to the first terminal of the antifuse during an active mode of operation when the antifuse is being read; and
coupling a second intermediate voltage between the read voltage and the supply voltage to the gate terminal of the high-voltage transistor during the active mode. - View Dependent Claims (2, 3, 4)
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5. A method of operating an antifuse circuit comprising:
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coupling an elevated voltage to a first terminal of an antifuse in an antifuse circuit during a programming mode of operation, the antifuse comprising a layer of gate dielectric between the first terminal and a second terminal;
bearing a portion of the elevated voltage on a high-voltage transistor coupled to the second terminal of the antifuse during the programming mode;
generating a first intermediate voltage at a gate terminal of the high-voltage transistor coupled to a first impedance and a second impedance, the first intermediate voltage being between the elevated voltage and a supply voltage during the programming mode to protect the high-voltage transistor, the first impedance being coupled between the first terminal of the antifuse and the gate terminal of the high-voltage transistor, and the second impedance being coupled between the supply voltage and the gate terminal of the high-voltage transistor;
coupling a read voltage to the first terminal of the antifuse during an active mode of operation when the antifuse is being read; and
generating a second intermediate voltage at the gate terminal of the high-voltage transistor during the active mode to be between the read voltage and the supply voltage. - View Dependent Claims (6, 7, 8)
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9. A method of operating an integrated circuit comprising:
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coupling an elevated voltage to a common bus line in an integrated circuit to program an antifuse in the integrated circuit during a programming mode of operation;
selecting a first antifuse in the integrated circuit to be programmed, the first antifuse being coupled to the common bus line;
bearing a portion of the elevated voltage on a second antifuse having a first terminal coupled to the common bus line in the integrated circuit, the second antifuse comprising a layer of gate dielectric between the first terminal and a second terminal;
bearing a portion of the elevated voltage on a high-voltage transistor coupled to the second terminal of the second antifuse during the programming mode;
coupling a first intermediate voltage between the elevated voltage and a supply voltage to a gate terminal of the high-voltage transistor to protect the high-voltage transistor during the programming mode;
coupling a read voltage to the common bus line during an active mode of operation when the second antifuse is being read; and
coupling a second intermediate voltage between the read voltage and the supply voltage to the gate terminal of the high-voltage transistor during the active mode. - View Dependent Claims (10, 11, 12)
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13. A method of operating a memory device comprising:
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accessing memory cells in an array of memory cells in a memory device by decoding address signals in an address decoder coupled to the array in the memory device;
coupling data to the memory cells through a plurality of input/output paths coupled to the array;
controlling the data on the input/output paths with an input/output control circuit;
coupling an elevated voltage to a first terminal of an antifuse in an antifuse circuit in the memory device during a programming mode of operation, the antifuse comprising a layer of gate dielectric between the first terminal and a second terminal;
bearing a portion of the elevated voltage on a high-voltage transistor coupled to the second terminal of the antifuse during the programming mode;
coupling a first intermediate voltage between the elevated voltage and a supply voltage to a gate terminal of the high-voltage transistor to protect the high-voltage transistor during the programming mode;
coupling a read voltage to the first terminal of the antifuse during an active mode of operation when the antifuse is being read; and
coupling a second intermediate voltage between the read voltage and the supply voltage to the gate terminal of the high-voltage transistor during the active mode. - View Dependent Claims (14, 15, 16, 17, 18)
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19. A method of operating a system comprising:
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exchanging signals between a processor and a memory system coupled together;
coupling an elevated voltage to a first terminal of an antifuse in an antifuse circuit in the memory system during a programming mode of operation, the antifuse comprising a layer of gate dielectric between the first terminal and a second terminal;
bearing a portion of the elevated voltage on a high-voltage transistor coupled to the second terminal of the antifuse during the programming mode;
coupling a first intermediate voltage between the elevated voltage and a supply voltage to a gate terminal of the high-voltage transistor to protect the high-voltage transistor during the programming mode;
coupling a read voltage to the first terminal of the antifuse during an active mode of operation when the antifuse is being read; and
coupling a second intermediate voltage between the read voltage and the supply voltage to the gate terminal of the high-voltage transistor during the active mode. - View Dependent Claims (20, 21, 22, 23, 24)
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Specification