STRUCTURE AND METHOD OF MAKING STRAINED SEMICONDUCTOR CMOS TRANSISTORS HAVING LATTICE-MISMATCHED SOURCE AND DRAIN REGIONS

• US 20050029601A1
• Filed: 08/04/2003
• Published: 02/10/2005
• Est. Priority Date: 08/04/2003
• Status: Active Grant

• Current Assignee: Semiconductor Manufacturing International Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Yang, Haining S., Chen, Huajie, Chidambarrao, Dureseti, Steegen, An L., Gluschenkov, Oleg G.
• Granted Patent: US 6,891,192 B2
• Time in Patent Office: Days
• US Class Current: 257/369
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02636 Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/0922 Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/66628 recessing the gate by forming single crystalline semiconductor material at the source or drain location
• CPC Class Codes: H01L 29/66636 with source or drain recessed by etching or first recessed by etching and then refilled
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain

Abstract

A p-type field effect transistor (PFET) and an n-type field effect transistor (NFET) of an integrated circuit are provided. A first strain is applied to the channel region of the PFET but not the NFET via a lattice-mismatched semiconductor layer such as silicon germanium disposed in source and drain regions of only the PFET and not of the NFET. A process of making the PFET and NFET is provided. Trenches are etched in the areas to become the source and drain regions of the PFET and a lattice-mismatched silicon germanium layer is grown epitaxially therein to apply a strain to the channel region of the PFET adjacent thereto. A layer of silicon can be grown over the silicon germanium layer and a salicide formed from the layer of silicon to provide low-resistance source and drain regions.

Claims

1. An integrated circuit having complementary metal oxide semiconductor (CMOS) transistors including a p-type field effect transistor (PFET) and an n-type field effect transistor (NFET), said PFET and said NFET each having a channel region and source and drain regions disposed in a first semiconductor region having a first composition, wherein a first strain is applied to said channel region of said PFET but not to said channel region of said NFET via second semiconductor regions having a second composition lattice-mismatched to said first semiconductor region, said second semiconductor regions underlying said source and drain regions of said PFET but not underlying said channel region of said PFET and not underlying said NFET.

3. The integrated circuit of claim 1 wherein said first semiconductor region has a main surface defined by a level of a gate dielectric of a gate stack of said PFET and said second semiconductor regions have top surfaces disposed beneath said main surface.

5. The integrated circuit of claim 1 wherein said first composition of said first semiconductor region is selected from the group consisting of silicon, silicon germanium and silicon carbide and said second composition of said second semiconductor regions is another composition different from said first composition, said another composition selected from the group consisting of silicon, silicon germanium and silicon carbide.

6. The integrated circuit of claim 1 wherein said first composition consists essentially of silicon and said second composition consists essentially of silicon germanium.

7. The integrated circuit of claim 1 wherein said first composition consists essentially of silicon germanium according to a first formula Si_x1Ge_y1, where x1 and y1 are percentages, x1+y1=100%, y1 being at least one percent and said second composition consists essentially of silicon germanium according to a second formula Si_x2Ge_y2, where x2 and y2 are percentages, x2+y2=100%, y2 being at least one percent, wherein x1 is not equal to x2 and y1 is not equal to y2.

8. The integrated circuit of claim 1 wherein said first strain is a compressive strain.

9. The integrated circuit of claim 6 wherein said second composition consists essentially of silicon germanium having a germanium content of at least one percent.

10. The integrated circuit of claim 1, further comprising silicide regions contacting gate conductors and said source regions and said drain regions of said PFET and said NFET.

11. The integrated circuit of claim 10 wherein said silicide regions consist essentially of a silicide of cobalt.

33. The integrated circuit of claim 1 wherein the second semiconductor regions are thin epitaxial layers disposed in trenches adjacent to said channel region of said NFET.

2. (canceled)

4. (canceled)

12. An integrated circuit having complementary metal oxide semiconductor (CMOS) transistors including a p-type field effect transistor (PFET) and an n-type field effect transistor (NFET), the NFET and the PFET each having a channel region and source and drain regions disposed in a first semiconductor region consisting essentially of silicon, wherein a first strain is applied to the channel region of the PFET but not to the channel region of the NFET via buried lattice-mismatched semiconductor regions consisting essentially of silicon germanium in underlying the source and drain regions of the PFET but not underlying the channel region of the PFET and not underlying the NFET, said silicon germanium of said buried lattice-mismatched semiconductor regions having proportions-a composition according to the formula Si_xGe_y where x and y are percentages each being at least one percent, x plus y equaling 100 percent.

13. A method of fabricating a p-type field effect transistor (PFET) and an n-type field effect transistor (NFET), said NFET and said PFET each having a channel region, said channel region of said PFET having a first strain and said channel region of said NFET not having said first strain, said method comprising:

forming a PFET gate stack and an NFET gate stack over a main surface of a single-crystal region of a first semiconductor, each of said PFET gate stack and said NFET gate stack including a gate dielectric, a gate conductor formed thereon, a cap layer formed over said gate conductor and first spacers formed on sidewalls of said gate conductor;

recessing said single-crystal region on sides of said PFET gate stack while protecting said main surface of said single-crystal region on sides of said NFET gate stack from being recessed;

growing a layer of a second semiconductor in areas of said single-crystal region exposed by said recessing while preventing said layer from growing on said single-crystal region on sides of said NFET gate stack, said second semiconductor being lattice-mismatched to said first semiconductor to apply said first strain to said channel region of said PFET; and

fabricating source and drain regions on said sides of said PFET gate stack to form said PFET and fabricating source and drain regions on said sides of said NFET gate stack to form said NFET.

14. The method of claim 13 further comprising recessing said layer of second semiconductor below said main surface of said single-crystal region.

15. The method of claim 14 further comprising growing a layer of said first semiconductor over said recessed second semiconductor layer.

16. The method of claim 15 further comprising forming a self-aligned silicide (salicide) over said source and drain regions of said PFET and of said NFET.

17. The method of claim 16 further comprising forming a self-aligned silicide (salicide) over polysilicon portions of said gate conductors of said PFET and said NFET.

18. The method of claim 17 wherein said silicide includes a silicide of cobalt.

19. The method of claim 15 wherein said first semiconductor comprises silicon and said second semiconductor comprises silicon germanium, said silicon germanium having a germanium content of at least one percent.

20. The method of claim 19 wherein said lattice-mismatched second semiconductor applies a compressive strain to said channel region of said PFET.

21. The method of claim 13 wherein said step of forming said source regions and drain regions further includes removing said first spacers from said PFET gate stack and said NFET gate stack and forming second spacers on sidewalls of said PFET gate stack and said NFET gate stack.

22. The method of claim 21 wherein said second spacers have a greater thickness than said first spacers.

23. The method of claim 21 further comprising halo implanting exposed areas of said single-crystal region and said layer of said first semiconductor.

24. The method of claim 21 further comprising extension implanting exposed areas of said single-crystal region and said layer of said first semiconductor.

25. The method of claim 22 further comprising forming third spacers laterally contacting said second spacers, and implanting source and drain regions in said exposed areas of said single-crystal region and said layer of said first semiconductor.

26. The method of claim 13 wherein said single-crystal region on said sides of said NFET gate stack are prevented from being recessed by a patterned block mask.

27. The method of claim 13 wherein said second semiconductor layer is prevented from growing on said single-crystal region on said sides of said NFET gate stack by applying a first coating to said single-crystal region on said sides of said NFET gate stack.

28. The method of claim 27 wherein said coating is formed conformally over an exposed surface of said single-crystal region including over said PFET gate stack and said NFET gate stack.

29. The method of claim 28 further comprising stopping said recessing of said single-crystal region on said sides of said PFET stack and forming a second coating on said areas of said single-crystal region exposed by said recessing, and thereafter continuing said recessing, such that said second semiconductor does not grow in areas protected by said second coating.

30. The method of claim 29 further comprising growing a layer of said first semiconductor on said layer of said second semiconductor.

31. The method of claim 30 wherein said first semiconductor comprises silicon and said second semiconductor comprises silicon germanium, said silicon germanium having a germanium content of at least one percent.

32. The method of claim 29 wherein said second semiconductor applies said first strain as a compressive strain.