High switching speed two mask schottky diode with high field breakdown

• US 20050029614A1
• Filed: 08/05/2003
• Published: 02/10/2005
• Est. Priority Date: 08/05/2003
• Status: Active Grant

• Current Assignee: Chip Integration Tech. Co., Ltd., Shye-Lin Wu
• Original Assignee: Chip Integration Tech. Co., Ltd.
• Inventors: Wu, Shye-Lin
• Granted Patent: US 6,998,694 B2
• Time in Patent Office: Days
• US Class Current: 257/471
• CPC Class Codes: H01L 29/0623 Buried supplementary region, e.g. buried guard ring multi-RESURF H01L29/0634
• CPC Class Codes: H01L 29/66143 Schottky diodes
• CPC Class Codes: H01L 29/872 Schottky diodes
• CPC Class Codes: H01L 29/8725 of the trench MOS barrier type [TMBS]

Abstract

A power Schottky rectifier device and its fabrication method are disclosed. The method comprises the following steps: First, a semiconductor substrate having a relatively heavily doped n+ doped layer and a lightly doped is provided. A buried p region is then formed in the epi layer by ion implantation. Afterward, a first oxide layer and a nitride layer are then successively formed on the epi layer. The result structure is then patterned to form trenches. Subsequently, a thermal oxidation step is performed to recover etch damage. A wet etch is then performed to remove the thin oxide layer in the trench to expose the silicon in the sidewall. After that, a silicidation process is then performed to form silicide layer on the n-epi-layer in the trenches. After a removal of un-reacted metal layer, a top metal layer is then formed on the silicide layer and on the first oxide layer or nitride layer. The top metal layer on the termination region portion is then patterned to define anode. Finally, after backside layers formed on the rear surface of the substrate are removed, another cathode layer is formed on the rear surface.

Claims

1-6. -6. (Canceled)

7. A power rectifier device, comprising:

a semiconductor substrate having a first conductive layer doped with first-type impurities, an epi layer formed thereon which is extended to a first surface thereof and is lightly doped with said first-type impurities;

a cathode metal layer formed on said first conductive layer opposite said first surface;

a first oxide layer formed on said first surface;

a pair of trenches formed through said first oxide layer and into a top of said epi-layer and spaced from each other by a first mesa region;

a termination mesa region surrounding said pair of cell trenches;

a second conductive type doped region formed into said epi layer of said first mesa region and said termination mesa region, wherein said first mesa region and said termination mesa region are regions located on said first surface having said first oxide layer formed thereon;

a Schottky barrier silicide layer formed on said epi layer located on bottom and side surfaces of said trenches;

a top metal layer acted acting as an anode and formed on said Schottky barrier silicide layer and extended to cover all surfaces of said first mesas region and a portion of said termination mesa region.

8. The power rectifier device according to claim 7 and further comprising a nitride layer formed in between said first oxide layer and said top metal layer.

9. The power rectifier device according to claim 8 wherein said first oxide layer has a thickness between about 100-1000 nm and said nitride layer has a thickness between about 50-300 nm.

10. The power rectifier device according to claim 8 wherein said trenches have a depth of between about 1 to 5 μ

m measured from the surface of said epi layer.

11. The power rectifier device according to claim 7 wherein said Schottky barrier silicide layer is formed of metal silicide selected from the group consisting of silicide of Ti, Ni, Cr, Mo, Pt, Zr, and W with silicon.

12. The power rectifier device according to claim 7 wherein said top metal layer is formed of stacked layers of TiNi/Ag or TiW/AI.