Structure and method of forming a dual-trench field effect transistor

• US 20050029618A1
• Filed: 09/03/2004
• Published: 02/10/2005
• Est. Priority Date: 01/30/2001
• Status: Abandoned Application

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Inventors: Marchant, Bruce D.
• Application Number:
  US10/934,969
• Publication Number:
  US 20050029618A1
• Time in Patent Office: Days
• US Class Current: 257/500
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A field effect transistor includes a semiconductor region of a first conductivity type and a well region of a second conductivity type over the semiconductor region. A source region of the first conductivity type is in an upper portion of the well region. A gate trench is adjacent to the source region. The gate trench extends through the well region and terminates within an upper half of the semiconductor region. A stripe trench extends through the well region and terminates within a lower half of the semiconductor region. The stripe trench is filled with a semiconductor material of the second conductivity type such that: (i) the filled stripe trench is contiguous with the well region, and (ii) the semiconductor material of the second conductivity type forms a PN junction with the semiconductor region.

Claims

1. A field effect transistor comprising:

a semiconductor region of a first conductivity type having a thickness defined by the distance between upper and lower surfaces of the semiconductor region;

a well region of a second conductivity type over the semiconductor region;

a source region of the first conductivity type in an upper portion of the well region;

a gate trench adjacent to the source region, the gate trench extending through the well region and terminating within an upper half of the semiconductor region; and

a stripe trench extending through the well region and terminating within a lower half of the semiconductor region at a depth above the bottom surface of the semiconductor region, the stripe trench being filled with a semiconductor material of the second conductivity type such that;

(i) the filled stripe trench is contiguous with the well region, and (ii) the semiconductor material of the second conductivity type forms a PN junction with the semiconductor region.

2. The field effect transistor of claim 1 wherein the depth at which the trip trench terminates is substantially near the bottom surface of the semiconductor region.

3. The field effect transistor of claim 2 wherein the gate trench terminates at a depth substantially near an interface between the semiconductor region and the well region.

4. The field effect transistor of claim 1 wherein the gate trench comprises a gate dielectric lining the trench sidewalls and a gate electrode comprising polysilicon at least partially filling the gate trench so as to overlap the source region along the vertical dimension.

5. The field effect transistor of claim 1 wherein the semiconductor region is an epitaxial layer extending over a substrate.

6. The field effect transistor of claim 1 wherein the stripe trench extends substantially deeper in the semiconductor region than does the gate trench.

7. The field effect transistor of claim 1 wherein the stripe trench terminates within a portion of the semiconductor region having a lower boundary which coincides with the lower surface of the semiconductor region and an upper boundary which is above the lower surface of the semiconductor region by a distance equal to one-third of the thickness of the semiconductor region.

8. The field effect transistor of claim 1 wherein the stripe trench is completely filled with the semiconductor material of the second conductivity type.

9. A field effect transistor comprising:

a semiconductor region of a first conductivity type having a thickness defined by the distance between upper and lower surfaces of the semiconductor region;

a well region of a second conductivity type over the semiconductor region;

a plurality of gate trenches each extending through the well region and terminating within an upper half of the semiconductor region;

a plurality of source regions of the first conductivity type in an upper portion of the well region, the plurality of source regions flanking the sides of the plurality of gate trenches; and

a plurality of stripe trenches each extending through the well region and terminating within a lower half of the semiconductor region at a depth above the bottom surface of the semiconductor region, each stripe trench being filled with a semiconductor material of the second conductivity type such that;

(i) the filled stripe trench is contiguous with the well region, and (ii) the semiconductor material of the second conductivity type forms a PN junction with the semiconductor region.

10. The field effect transistor of claim 9 wherein the depth at which the plurality of stripe trenches terminate is substantially near a bottom surface of the semiconductor region.

11. The field effect transistor of claim 10 wherein the plurality of gate trenches terminate at a depth substantially near an interface between the semiconductor region and the well region.

12. The field effect transistor of claim 9 wherein each of the plurality of gate trenches comprises:

a gate dielectric lining the trench sidewalls; and

a gate electrode comprising polysilicon at least partially filling the gate trench so as to overlap source regions flanking each side of the gate trench.

13. The field effect transistor of claim 9 wherein the semiconductor region is an epitaxial layer extending over a substrate.

14. The field effect transistor of claim 9 wherein the plurality of stripe trenches extend substantially deeper into the semiconductor region than do the gate trenches.

15. The field effect transistor of claim 9 wherein the plurality of stripe trenches terminate within a portion of the semiconductor region having a lower boundary which coincides with the lower surface of the semiconductor region and an upper boundary which is above the lower surface of the semiconductor region by a distance equal to one-third of the thickness of the semiconductor region.

16. The field effect transistor of claim 9 wherein the plurality of stripe trenches are spaced from one another and extend to such depth within the semiconductor region that upon applying a reverse voltage across a junction between the well region and the semiconductor region a substantial portion of the entire semiconductor region, including those portions of the semiconductor region between adjacent stripe trenches, becomes depleted of charge carriers.

17. The field effect transistor of claim 10 wherein each of the plurality of stripe trenches is completely filled with the semiconductor material of the second conductivity type.

18. A method of forming a field effect transistor comprising:

forming a well region in a semiconductor region of a first conductivity type, the well region being of a second conductivity type and having an upper surface and a lower surface;

forming a plurality of gate trenches extending into the semiconductor region to a depth below the lower surface of the well region;

forming a plurality of stripe trenches extending through the well region and into the semiconductor region to a depth below that of the plurality of gate trenches, the plurality of stripe trenches being laterally spaced from one or more of the plurality of gate trenches; and

at least partially filling the plurality of stripe trenches with a semiconductor material of the second conductivity type such that the semiconductor material of the second conductivity type forms a PN junction with a portion of the semiconductor region.

19. The method of claim 18 wherein the plurality of stripe trenches extend into the semiconductor region parallel to a current flow through the semiconductor region when the field effect transistor is in an on state.

20. The method of claim 18 wherein the plurality of stripe trenches are completely filled with the semiconductor material of the second conductivity type using selective epitaxial growth.

21. The method of claim 18 wherein the semiconductor material of the second conductivity type lines the sidewalls of the plurality of stripe trenches, the method further comprising:

forming a dielectric material within the plurality of stripe trenches such that each stripe trench becomes substantially completely filled with the combination of the semiconductor material of the second conductivity type and the dielectric material.

22. The method of claim 18 wherein the plurality of stripe trenches are formed after forming the plurality of gate trenches and the well region.

23. The method of claim 18 wherein the semiconductor region is an epitaxial layer of the first conductivity type in which the well region is formed, the epitaxial layer having a thickness defined by the spacing between an upper surface and a lower surface of the epitaxial layer, wherein the plurality of stripe trenches extend into the epitaxial layer and terminate at a depth between one-half the thickness of the epitaxial layer and the lower surface of the epitaxial layer.

24. The method of claim 18 wherein the semiconductor region has a thickness defined by the vertical distance between an upper surface and a lower surface of the semiconductor region, the plurality of stripe trenches terminating within a portion of the semiconductor region having a lower boundary which coincides with the lower surface of the semiconductor region and an upper boundary which is above the lower surface of the semiconductor region by a distance equal to one-third of the thickness of the semiconductor region.

25. The method of claim 20 further comprising forming source regions in the well region.

26. The method of claim 25 wherein the semiconductor region comprises an epitaxial layer and a substrate both of the first conductivity type, the substrate forming a drain contact region, the method further comprising:

forming the epitaxial layer over the substrate, the well region being formed in the epitaxial layer, and the plurality of stripe trenches and gate trenches extending into and terminating within the epitaxial layer.