Barrier-less integration with copper alloy

• US 20050029665A1
• Filed: 09/08/2004
• Published: 02/10/2005
• Est. Priority Date: 01/24/2003
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Liang, Mong-Song, Shue, Shau-Lin, Hsieh, Ching-Hua, Huang, Cheng-Lin, Lin, Jing-Cheng
• Granted Patent: US 7,215,024 B2
• Time in Patent Office: Days
• US Class Current: 257/762
• CPC Class Codes: H01L 21/32051 Deposition of metallic or metal-silicide layers
• CPC Class Codes: H01L 21/32136 using plasmas
• CPC Class Codes: H01L 21/76843 formed in openings in a dielectric
• CPC Class Codes: H01L 21/76844 Bottomless liners
• CPC Class Codes: H01L 21/76846 Layer combinations
• CPC Class Codes: H01L 21/76855 After-treatment introducing at least one additional element into the layer
• CPC Class Codes: H01L 21/76877 Filling of holes, grooves or trenches, e.g. vias, with conductive material
• CPC Class Codes: H01L 21/76888 By rendering at least a portion of the conductor non conductive, e.g. oxidation
• CPC Class Codes: H01L 23/53238 Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 23/53295 Stacked insulating layers
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A new method is provided for the creation of a barrier-free copper interconnect. A dual damascene structure is created in a layer of dielectric, a thin metal barrier layer is deposited. The metal barrier layer is oxidized, two layers are then deposited with the first layer comprising doped copper and the second layer comprising pure copper. The dual damascene structure is filled with copper, a thermal anneal is applied, stabilizing the deposited copper filling the dual damascene structure and forming metal oxide of the doped minority element. Excess copper is then removed from the dielectric.

Claims

1. A copper interconnect, comprising:

a substrate, the substrate comprising semiconductors in or over the substrate, the substrate further comprising at least one contact point of first level copper;

at least one interconnect opening through layers of semiconductor material over the substrate aligned with the at least one contact point;

sidewalls of the at least one interconnect opening lined with an annealed compound layer, comprising;

(i) a layer of metal barrier material

(ii) a layer of metal barrier material oxide created over the surface there-of;

(ii) a layer of doped copper; and

(iii) a layer of pure copper; and

the at least one interconnect opening filled with copper.

2. The copper interconnect of claim 1, the layers of semiconductor material comprising at least one layer of etch stop material and at least one layer of low-k dielectric.

3. The copper interconnect of claim 1, the interconnect openings having a profile selected from the group of profiles consisting of single damascene profile and a dual damascene profile and a contact opening profile and via opening profile.

4. The copper interconnect of claim 1, the layer of metal barrier material being selected from the group consisting of Ta and TaN and TiN.

5. The copper interconnect of claim 1, the doped copper comprising a doping element selected from the group consisting of Cr, Pd, Sn, Ti, Zr, Mg, Al.

6. The copper interconnect of claim 1, the doped copper layer having a thickness of between about 50 and 300 Angstrom.

7. The copper interconnect of claim 1, the layer of metal barrier material layer having a thickness of between 30 and 150 Angstrom.

8. The copper interconnect of claim 1, the pure copper layer having a thickness of between about 300 and 1,000 Angstrom.