Apparatus and method for packaging circuits

• US 20050029668A1
• Filed: 08/30/2004
• Published: 02/10/2005
• Est. Priority Date: 10/08/2001
• Status: Active Grant

• Current Assignee: Round Rock Research LLC
• Original Assignee: Micron Technology, Inc.
• Inventors: Jeung, Boon Suan, Poo, Chia Yong, Loo, Neo Yong, Koon, Eng Meow, Kwang, Chua Swee, Waf, Low Siu, Yu, Chan Min, Leng, Ser Bok, Chung, So Chee, Seng, Ho Kwok
• Granted Patent: US 8,138,617 B2
• Time in Patent Office: Days
• US Class Current: 257/773
• CPC Class Codes: H01L 21/78 with subsequent division of the substrate into plural individual devices cutting to change the surface-physical characteristics or shape of semiconductor bodies H01L21/304
• CPC Class Codes: H01L 2224/0231 Manufacturing methods of the redistribution layers
• CPC Class Codes: H01L 2224/02311 Additive methods
• CPC Class Codes: H01L 2224/02313 Subtractive methods
• CPC Class Codes: H01L 2224/02331 Multilayer structure
• CPC Class Codes: H01L 2224/02371 connecting the bonding area on a surface of the semiconductor or solid-state body with another surface of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/02375 Top view
• CPC Class Codes: H01L 2224/02379 Fan-out arrangement
• CPC Class Codes: H01L 2224/0239 Material of the redistribution layers
• CPC Class Codes: H01L 2224/03 Manufacturing methods
• CPC Class Codes: H01L 2224/0345 Physical vapour deposition [PVD], e.g. evaporation, or sputtering
• CPC Class Codes: H01L 2224/03452 Chemical vapour deposition [CVD], e.g. laser CVD
• CPC Class Codes: H01L 2224/0361 Physical or chemical etching
• CPC Class Codes: H01L 2224/03622 using masks
• CPC Class Codes: H01L 2224/039 Methods of manufacturing bonding areas involving a specific sequence of method steps
• CPC Class Codes: H01L 2224/05548 Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05552 in top view
• CPC Class Codes: H01L 2224/05569 the external layer being disposed on a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05571 the external layer being disposed in a recess of the surface
• CPC Class Codes: H01L 2224/05572 the external layer extending out of an opening
• CPC Class Codes: H01L 2224/056 : with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/08237 : the bonding area connecting to a bonding area disposed in a recess of the surface of the item
• CPC Class Codes: H01L 2224/80357 : being flush with the surface
• CPC Class Codes: H01L 2224/804 : with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/80898 : Press-fitting, i.e. pushing the parts together and fastening by friction, e.g. by compression of one part against the other
• CPC Class Codes: H01L 2224/93 : Batch processes
• CPC Class Codes: H01L 24/03 : Manufacturing methods
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/08 : of an individual bonding area
• CPC Class Codes: H01L 24/80 : Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
• CPC Class Codes: H01L 24/93 : Batch processes
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 : Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/05042 : Si3N4
• CPC Class Codes: H01L 2924/10156 : at the periphery
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15153 : the die mounting substrate comprising a recess for hosting the device
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H10B 99/22 : including field-effect components

Abstract

Methods for forming an edge contact on a die and edge contact structures are described. The edge contacts on the die do not increase the height of the die. The edge contacts are positioned on the periphery of a die. The edge contacts are positioned in the saw streets. Each edge contact is connected to one bond pad of each die adjacent the saw street. The edge contact is divided into contacts for each adjacent die when the dies are separated. In an embodiment, a recess is formed in the saw street. In an embodiment, the recess is formed by scribing the saw street with a mechanical cutter. The recess is patterned and contact material is deposited to form the edge contacts.

Claims

1. An electrical system, comprising:

a first circuit having first contacts, and

a die having an integrated circuit formed therein, wherein the die includes;

a main body including a top layer, a bottom layer, and a peripheral edge surface extending between the top layer and the bottom layer;

a bond pad on the main body;

an edge contact at the peripheral edge surface, the edge contacts being in electrical communication with the first contacts; and

a line connecting the bond pad to the edge contact.

2. The electrical system of claim 1, wherein the edge contacts are in physical contact with the first contacts.

3. The electrical system of claim 2, wherein the integrated circuit includes a memory device.

4. The electrical system of claim 3, wherein the memory device includes one of a DRAM, SRAM, SDRAM, EEPROM, and flash memory.

5. The electrical system of claim 4, wherein the first circuit includes a communication bus.

6. The electrical system of claim 5, wherein the first circuit includes a processor.

7. The electrical system of claim 2, wherein the main body has a first height, and the edge contact as a second height, and the second height is less than the first height.

8. The electrical system of claim 2, wherein the main body has a first height, and the edge contact as a second height, and the second height is essentially equal to the first height.

9. The electrical system of claim 1, wherein the bond pad is at the top layer.

10. The electrical system of claim 11, wherein the edge contact is beneath the top layer.

11. The electrical system of claim 1, wherein the edge contact is above a bottom surface of the bottom layer such that the edge contact does not increase a height of the die.

12. The electrical system of claim 1, wherein the edge contact includes at least one of copper, gold, or silver.

13. The electrical system of claim 1, wherein the bond pad is at the top layer.

14. A system comprising a land pattern, integrated circuit package and an electrical device, wherein the package includes:

a die including a top layer, a bottom layer, and a peripheral edge surface extending between the top layer and the bottom layer;

a bond pad on the die;

an edge contact at the peripheral edge surface; and

a line connecting the bond pad to the edge contact;

wherein the electrical device includes a device contact providing electrical contact between the electrical device and the die through the edge contact.

15. The system of claim 14, wherein the electrical device includes a socket with the device contact positioned therein, the socket being dimensioned to receive the die.

16. The system of claim 15, wherein the package further includes an encapsulant enclosing the die, and wherein the edge contact extends outside the encapsulant.

17. The system of claim 16, wherein the encapsulant encloses the bond pad and the line.

18. The system of claim 14, wherein the edge contact is beneath the top layer.

19. The system of claim 14, wherein the edge contact is above the bottom layer such that the edge contact does not increase the height of the die.

20. The system of claim 14, wherein the bond pad is at the top layer.

21. The system of claim 14, wherein the die includes a plurality of the at least one edge contacts.

22. The system of claim 14, wherein the die includes saw street and the at least one edge contact is positioned in the saw street.

23. The system of claim 14, wherein the edge contact is beneath the top layer.

24. The system of claim 14, wherein the edge contact includes a metallic coating.

25. The system of claim 24, wherein the metallic coating includes at least one of silver and gold.

26. The system of claim 14, wherein the main body includes an insulative coating on the bond pad and the line.

27. The system of claim 26, wherein the insulative coating includes at least one of benzocyclobutenes and polymides.

28. An electrical system, comprising a first integrated circuit, a second integrated circuit, and a bus operably connecting the first integrated circuit and the second integrated circuit, wherein the first integrated circuit includes:

a main body including a top layer, a bottom layer, and a peripheral edge surface extending between the top layer and the bottom layer;

a bond pad on the main body;

an edge contact at the peripheral edge surface, the edge contact having an outer peripheral surface remote from the main body and an inner surface adjacent the main body, wherein the outer peripheral surface is essentially coplanar with the edge surface of the main body; and

a line connecting the bond pad to the edge contact.

29. The electrical system of claim 28, wherein the first integrated circuit includes a memory device and the second integrated circuit includes a processor.

30. The electrical system of claim 28, wherein the bond pad is at the top layer.

31. The electrical system of claim 28, wherein the edge contact includes a metallic coating.

32. The electrical system of claim 31, wherein the metallic coating includes at least one of silver and gold.

33. A method, comprising:

fabricating at least two dies on a wafer, wherein the at least two dies are joined at a saw street;

forming a recess in the saw street;

filling the recess with an electrically conducting material;

connecting a bond pad from at least one of the dies to the electrically conductive material; and

separating the at least two dies from each other along the saw street.

34. The method of claim 33 wherein the fabricating at least two dies includes fabricating circuits for a memory device on at least one of the dies.

35. The method of claim 33, wherein forming the recess includes sawing along the saw street to a depth of about half a height of the die.

36. The method of claim 33, wherein connecting the bond pad includes depositing a metal on the wafer between the bond pad and the electrically conductive material.

37. A method, comprising:

patterning a recess in a saw street intermediate adjacent dies in a wafer;

depositing an electrically conductive material in the recess to form an edge contact;

connecting a bond pad of both dies to the edge contact; and

separating the adjacent dies along the saw street such that each dies includes a part of the edge contact.

38. The method of claim 37, wherein pattering the recess includes masking the wafer such that the electrically conductive material is deposited only in the recess.

39. The method of claim 38, wherein the patterning includes masking the recess such that the electrically conductive material forms a plurality of individual edge contacts.

40. The method of claim 39, further comprising extending the recess the length of the saw street.