Multiplex bus interface system and method for transmitting and receiving power and data

• US 20050030165A1
• Filed: 04/07/2004
• Published: 02/10/2005
• Est. Priority Date: 12/08/1999
• Status: Active Grant

• Current Assignee: Ed&D Technologies, LLC
• Original Assignee: ED&D, Inc.
• Inventors: Bush, Matthew, Bateman, David E.
• Granted Patent: US 7,057,496 B2
• Time in Patent Office: Days
• US Class Current: 370/294
• CPC Class Codes: H04B 2203/5408 using protocols
• CPC Class Codes: H04B 2203/5416 by adding signals to the wave form of the power source
• CPC Class Codes: H04B 2203/5458 Monitor sensor; Alarm systems
• CPC Class Codes: H04B 2203/547 via DC power distribution
• CPC Class Codes: H04B 3/548 the power on the line being DC arrangements for feeding power H04L12/10; extracting feeding power from signals H04L25/02

Abstract

A multiplex bus interface enables power and data to be transmitted and received on a two wire bus. Input and output devices operate with transceivers connected to the bus to communicate with each other by placing their data on the bus within specific time slots controlled by a controller, a clock module which broadcasts data to all connected transceivers. A pulsed power waveform provides power to the transceivers and data through pulse width modulation of the pulsed waveform. Data from the transceivers is transmitted during a time slot between power pulses. Data integrity is checked by the initiating input transceiver. Errors are reported at the end of a broadcast cycle. Output transceivers use the data as appropriate for the device and condition being monitored or controlled.

Claims

1. A communications and control system comprising:

a transceiver for transmitting and receiving an electrical signal; and

a controller operable with the transceiver for controlling power and data delivered thereto, wherein the power to the transceiver is controlled through a waveform having a plurality of pulses separated by a time slot with the power delivered with each pulse and absent during the time slot for transmitting data therein, and wherein the controller provides control data signals to the transceiver through a pulse width modulation of the waveform, with a first pulse width of the pulse representing a first data value and a second pulse width thereof representing a second data value, the transceiver providing data output within the time slot, and thus full duplex operation with bi-directional communication between the controller and the transceiver.