Apparatus and method for distributed memory control in a graphics processing system

• US 20050030313A1
• Filed: 08/31/2004
• Published: 02/10/2005
• Est. Priority Date: 06/23/2000
• Status: Active Grant

• Current Assignee: Round Rock Research LLC
• Original Assignee: James Richard Peterson, William Radke
• Inventors: Peterson, James R., Radke, William
• Granted Patent: US 7,180,522 B2
• Time in Patent Office: Days
• US Class Current: 345/532
• CPC Class Codes: G06F 13/1657 Access to multiple memories
• CPC Class Codes: G09G 2360/121 using a cache memory
• CPC Class Codes: G09G 5/363 Graphics controllers
• CPC Class Codes: G09G 5/393 Arrangements for updating the contents of the bit-mapped memory

Abstract

A distributed memory controller memory system for a graphics processing system having addressable memory areas each coupled to a respective memory controller. The memory controllers are further coupled to each other through a memory controller bus upon which a memory access request and data may be passed from one memory controller to other memory controller. A memory access request to a memory location in one addressable memory area, but received by a memory controller coupled to another addressable memory area, is passed through the memory controller bus from the receiving memory controller to the memory controller coupled to the addressable memory area in which the requested location is located in order to service the memory access request. Additional memory controllers coupled to a respective addressable memory area may be included in the memory system. The memory controllers are coupled to the memory controller bus in order to receive and pass memory access requests from the other memory controllers.

Claims

1. A memory system for a graphics processing system having a memory request bus to provide a direct memory access request to access memory, the direct memory access request including a memory address corresponding to a location in memory to be accessed, the memory system comprising:

a first addressable memory area defined by a first start address and a first size value to store graphics data;

a first memory controller coupled to the first addressable memory area and having a start address register and a memory size register for storing, respectively, the first start address and the first size value, the first memory controller coupled to the memory request bus to receive the direct memory access request and adapted to access the first addressable memory area in response to the memory address being located therein and to generate an indirect memory access request including the memory address otherwise;

a memory controller bus coupled to the first memory controller structured to transmit the indirect memory access request and to transmit graphics data;

a second addressable memory area defined by a second start address and a second size value to store graphics data; and

a second memory controller coupled to the second addressable memory area and having a start address register and a memory size register for storing respectively, the second start address and the second size value, the second memory controller further coupled to the memory controller bus to receive the indirect memory access request from the first memory controller and adapted to access the second addressable memory area in response to the memory address being located therein to service the direct memory access request received by the first memory controller.

2-52. -52. (Cancelled)