Method and system for dynamically allocating a frame buffer for efficient anti-aliasing

• US 20050030314A1
• Filed: 09/14/2004
• Published: 02/10/2005
• Est. Priority Date: 11/15/2000
• Status: Active Grant

• Current Assignee: Thomas P. Dawson
• Original Assignee: Thomas P. Dawson
• Inventors: Dawson, Thomas P.
• Granted Patent: US 7,034,846 B2
• Time in Patent Office: Days
• US Class Current: 345/536
• CPC Class Codes: G06T 1/60 Memory management
• CPC Class Codes: G06T 11/40 Filling a planar surface by adding surface attributes, e.g. colour or texture
• CPC Class Codes: G06T 15/005 General purpose rendering architectures
• CPC Class Codes: G06T 15/405 using Z-buffer
• CPC Class Codes: G06T 2200/12 involving antialiasing

Abstract

A polygon rendering system for receiving geometric data defining a polygon in an image being generated. The polygon rendering system renders the geometric data as pixel data. The pixel data defines pixels used to display the image. The system comprises a first memory buffer for storing the pixel data. It also comprises a second memory buffer for storing additional pixel data used to render edge pixels at a higher resolution than pixels that are not the edge pixels. Edge pixels are pixels that are located on an edge of the polygon in the image. The system also comprises a display controller for outputting the pixel data in the first memory buffer to output circuitry. The polygon rendering system identifies which of the pixels are the edge pixels and the display controller updates contents of the first buffer with data based on contents of the second buffer. The additional pixel data is used to compute a color value for the edge pixels and comprises a cluster of sub-pixel data for each of the edge pixels of the image. The sub-pixel data defines a number of sub-pixels and comprises a color value for each of the sub-pixels in the cluster. The display controller computes a color value for the edge pixels based on an average of the color values for each of the sub-pixels in each cluster that corresponds to the edge pixels and stores the computed color value in a field corresponding to the edge pixels in the first buffer.

Claims

1. A polygon rendering system for receiving geometric data defining a polygon in an image being generated and rendering said geometric data as pixel data, said pixel data defining pixels used to display said image, said system comprising:

a first memory buffer for storing said pixel data;

a second memory buffer for storing additional pixel data used to render edge pixels at a higher resolution than pixels that are not said edge pixels, said edge pixels located on an edge of said polygon in said image; and

a display controller for outputting said pixel data in said first memory buffer to output circuitry;

wherein said polygon rendering system identifies which of said pixels are said edge pixels and said display controller updates contents of said first buffer with data based on contents of said second buffer.

2. The system of claim 1, wherein said display controller allocates memory to said second buffer as needed to store more of said additional pixel data as additional polygons are generated.

3. The system of claim 1, wherein said display controller includes a register for storing a starting address of said second buffer.

4. The system of claim 1, wherein said display controller stores a starting address of said second buffer in a third memory buffer of said polygon rendering system.

5. The system of claim 1, wherein said first buffer comprises at least three data fields for each of said pixels, said three data fields comprising:

a bit flag field containing a hi-res bit flag indicating whether said field'"'"'s corresponding pixel is one of said edge pixels;

a color data field containing a color value for said corresponding pixel; and

Z-distance field containing a Z-distance value for said corresponding pixel.

6. The system of claim 5, wherein, when said polygon rendering system renders pixel data defining an edge pixel, said display controller writes a memory offset value in a data field corresponding to said edge pixel in said first buffer, said memory offset value indicating an address of said additional pixel data corresponding to said edge pixel in said second buffer.

7. The system of claim 6, wherein said data field is said Z-distance field.

8. The system of claim 1, wherein said system further comprises a rasterizer unit for processing said geometric data and identifying said edge pixels.

9. The system of claim 5, wherein said additional pixel data stored in said second buffer comprises a cluster of sub-pixel data for each of said edge pixels of said image, said sub-pixel data defining a number of sub-pixels.

10. The system of claim 9, wherein said sub-pixel data comprises a color value for each of said number of sub-pixels.

11. The system of claim 10, wherein said display controller computes a color value for said edge pixel, said color value based on an average of said color values for each of said number of sub-pixels in a cluster corresponding to said edge pixel.

12. The system of claim 11, wherein said display controller writes said averaged color value in a color data field in said first buffer, said field associated with said edge pixel.

13. The system of claim 5, wherein said number of sub-pixels is four.

14. The system of claim 13, wherein said four sub-pixels are arranged in a two by two array of sub-pixels.

15. The system of claim 5, wherein said number of sub-pixels is sixteen.

16. The system of claim 15, wherein said sixteen sub-pixels are arranged in a four by four array of sub-pixels.

17. The system of claim 11, wherein:

said each of said number of sub-pixels, a majority of which is located within said polygon in said image, is rendered as a pixel wholly internal to said polygon; and

said each of said number of sub-pixels, a majority of which is located outside said polygon in said image, is rendered as a background pixel and assigned a color value equal to a color value of said background.

18. The system of claim 17, wherein said second buffer comprises at least three data fields for said each of said number of sub-pixels, said three data fields comprising:

a color data field containing a color value for a corresponding sub-pixel;

a Z-distance field containing a Z-distance value for said corresponding sub-pixel; and

a bit flag field containing a bit indicating, for each of said sub-pixels, whether said corresponding sub-pixel'"'"'s color value is used in said computation of said averaged color value or whether said color value of said background is used in said computation of said averaged color value.

19. The system of claim 17, wherein said second buffer comprises:

a single Z-distance field for said cluster of sub-pixel data, said Z-distance field containing a Z-distance value for said edge pixel;

a color data field for each of said sub-pixels in said cluster of sub-pixel data, said color data field containing a color value for a corresponding sub-pixel; and

a bit flag mask field for said cluster of sub-pixel data, said bit flag mask field containing a number of bits equaling said number of sub-pixels in said cluster, said bits indicating whether color values of corresponding sub-pixels are used in said computation of said averaged color value or whether said color value of said background is used in said computation of said averaged color value.

20. The system of claim 1, wherein said first and second buffers are integrated into a single physical memory unit.

21. The system of claim 1, wherein said first and second buffers are separate physical memory units.

22. The system of claim 1, wherein said first and second buffers are contained within a physical memory unit used by a host central processing unit.

23. The system of claim 1, wherein said first and second buffers are contained within a physical memory unit separate from a physical memory unit used by a host central processing unit.

24. The system of claim 1, wherein said polygon rendering system is an application specific integrated circuit, field-programmable gate array, digital signal processor, or an integrated circuit.

25. The system of claim 1, wherein said output circuitry is a video signal generator connected to a display monitor.

26. The system of claim 1, wherein said output circuitry is a printer.

27. A rasterizer unit, said rasterizer unit configured to:

render geometric data as pixel data, said geometric data defining a polygon in an image being generated, said pixel data defining pixels used to display said image; and

identify an edge pixel located on an edge of said polygon;

wherein, when said rasterizer unit identifies said edge pixel, said rasterizer unit outputs data that signals a display controller to allocate memory to a second memory buffer for storage of additional pixel data used to render said edge pixel at a higher resolution than pixels that are not said edge pixels, said second buffer in addition to a first memory buffer for storing said pixel data.

28. The rasterizer unit of claim 27, wherein said first and second buffers are integrated into a single physical memory unit.

29. The rasterizer unit of claim 27, wherein said first and second buffers are separate physical memory units.

30. The rasterizer unit of claim 27, wherein said first and second buffers are contained within a physical memory unit used by a host central processing unit.

31. The rasterizer unit of claim 27, wherein said first and second buffers are contained within a physical memory unit separate from a physical memory unit used by a host central processing unit.

32. The rasterizer unit of claim 27, wherein said rasterizer unit is a discrete component.

33. The rasterizer unit of claim 32, wherein said discrete component is an application specific integrated circuit, field-programmable gate array, digital signal processor, or an integrated circuit.

34. The rasterizer unit of claim 27, wherein said rasterizer unit is integrated in a polygon rendering system.

35. The rasterizer unit of claim 34, wherein said polygon rendering system is a discrete component.

36. The rasterizer unit of claim 35, wherein said polygon rendering system is an application specific integrated circuit, field-programmable gate array, digital signal processor, or an integrated circuit.

37. The rasterizer unit of claim 27, wherein said rasterizer unit comprises a bit flag cache having a memory location to store a bit flag corresponding to each pixel in said image;

and

said rasterizer unit stores a hi-res bit flag value in said bit flag cache for each pixel in said image, said hi-res bit flag indicating whether said pixel is an edge pixel.

38-101. -101. (cancelled)