Contact structure of conductive films and thin film transistor array panel including the same

• US 20050030465A1
• Filed: 06/25/2004
• Published: 02/10/2005
• Est. Priority Date: 06/27/2003
• Status: Active Grant

• Current Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Kong, Hyang-Shik, Kim, Dong-Gyu, Hur, Myung-Koo, Chang, Jong-Woong, Lee, Seong-Young, Park, Myung-Jae
• Granted Patent: US 7,714,820 B2
• Time in Patent Office: Days
• US Class Current: 349/149
• CPC Class Codes: G02F 1/1345 Conductors connecting electrodes to cell terminals
• CPC Class Codes: G02F 1/13458 Terminal pads

Abstract

A thin film transistor array panel is provided, which includes: a display cell array circuit including a plurality of gate lines, a plurality of data lines, a plurality of thin film transistors, and a plurality of pixel electrodes; a gate driving circuit supplying gate signals to the gate lines; and a signal line connected to the gate driving circuit and including first and second line segments separated from each other and a connection member connected to the first and second line segments through at least a contact hole exposing at least one of the first and the second line segments.

Claims

1. A thin film transistor array panel, comprising:

a display cell array circuit including a plurality of gate lines, a plurality of data lines, a plurality of thin film transistors, and a plurality of pixel electrodes;

a gate driving circuit supplying gate signals to the gate lines; and

a signal line connected to the gate driving circuit and including first and second line segments separated from each other and a connection member connected to the first and second line segments through at least a contact hole exposing at least one of the first and the second line segments,

wherein the at least a contact hole has a petallike or serpentine boundary.

2. The thin film transistor array panel of claim 1, wherein the first and second line segments are disposed on different layers.

3. The thin film transistor array panel of claim 2, further comprising:

a first insulating layer formed on the first line segment,

wherein the at least contact hole includes a first contact hole provided at the first insulating layer and exposing the first line segment at least in part.

4. The thin film transistor array panel of claim 3, wherein the first contact hole exposes an edge of the first line segment.

5. The thin film transistor array panel of claim 4, wherein the exposed edge of the first line segment is petallike or serpentine.

6. The thin film transistor array panel of claim 3, wherein the first line segment includes a lower film and an upper film on the lower film.

7. The thin film transistor array panel of claim 6, wherein the lower film includes Al, Al alloy, Ag or Ag alloy and the upper film includes Cr, Mo, Ti or Ta.

8. The thin film transistor array panel of claim 7, wherein the first contact hole exposes the lower film of the first line segment.

9. The thin film transistor array panel of claim 3, further comprising:

a second insulating layer formed on the second line segment,

wherein the at least a contact hole further includes a second contact hole provided at the first and the second insulating layer and exposing the second line segment at least in part and the connection member is formed on the second insulating layer and connected to the first and the second line segments through the first and the second contact holes, respectively.

10. The thin film transistor array panel of claim 1, wherein the first line segment includes the same layer as the gate lines or the data lines.

11. The thin film transistor array panel of claim 1, wherein the connection member includes the same layer as the pixel electrodes.

12. The thin film transistor array panel of claim 1, wherein the connection member includes the same layer as the gate lines or the data lines.

13. The thin film transistor array panel of claim 1, wherein the gate driving circuit comprises a shift register including a plurality of stages connected in sequence and the signal line transmits one of a plurality of clock signals having phase shifts, and a voltage.

14. The thin film transistor array panel of claim 1, further comprising a data driving circuit supplying data signals to the data lines.

15. A thin film transistor array panel, comprising:

a display cell array circuit including a plurality of gate lines, a plurality of data lines, a plurality of thin film transistors, and a plurality of pixel electrodes;

a gate driving circuit supplying gate signals to the gate lines; and

a signal line connected to the gate driving circuit and including first and second line segments separated from each other and a connection member connected to the first and second line segments through at least a contact hole exposing at least one of the first and the second line segments,

wherein edges of the first and the second line segments are toothed and engage with each other.

16. The thin film transistor array panel of claim 15, wherein the first and second line segments are disposed on different layers.

17. The thin film transistor array panel of claim 16, wherein the at least contact hole includes a first contact hole exposing the first line segment at least in part.

18. The thin film transistor array panel of claim 17, wherein the first contact hole exposes an edge of the first line segment.

19. The thin film transistor array panel of claim 17, wherein the first contact hole further exposes the second line segment at least in part.

20. The thin film transistor array panel of claim 17, wherein the at least contact hole further includes a second contact hole exposing the second line segment at least in part.

21. The thin film transistor array panel of claim 15, wherein the first line segment includes the same layer as the gate lines or the data lines.

22. The thin film transistor array panel of claim 15, wherein the connection member includes the same layer as the pixel electrodes.

23. The thin film transistor array panel of claim 15, wherein the connection member includes the same layer as the gate lines or the data lines.

24. A contact structure of conductive films, the contact structure comprising:

first and second conductive layers;

an insulator formed on the first conductive layer and having a contact hole exposing the first conductive layer at least in part; and

a connection member formed on the insulator and connected to the first conductive layer through the contact hole and to the second conductive layer,

wherein an edge of at least one of the contact hole, the first conductive layer and the second conductive layer is petallike or serpentine.

25. The contact structure of claim 24, wherein the contact hole exposes an edge of the first conductive layer.

26. The contact structure of claim 25, wherein the exposed edge of the first conductive layer is petallike or serpentine.

27. The contact structure of claim 24, wherein the first and the second line segments have toothed edges engaging with each other.

28. The contact structure of claim 24, wherein the contact hole further exposes the second line segment at least in part.