Circuit and method for refreshing memory cells of a dynamic memory

• US 20050030807A1
• Filed: 06/30/2004
• Published: 02/10/2005
• Est. Priority Date: 06/30/2003
• Status: Active Grant

• Current Assignee: Polaris Innovations Limited (Wi-LAN Inc.)
• Original Assignee: Qimonda AG (Infineon Technologies AG)
• Inventors: Perner, Martin
• Granted Patent: US 6,999,369 B2
• Time in Patent Office: Days
• US Class Current: 365/222
• CPC Class Codes: G11C 11/406 Management or control of the refreshing or charge-regeneration cycles
• CPC Class Codes: G11C 11/40611 External triggering or timing of internal or partially internal refresh operations, e.g. auto-refresh or CAS-before-RAS triggered refresh
• CPC Class Codes: G11C 11/40622 Partial refresh of memory arrays

Abstract

A circuit for refreshing memory cells of a dynamic memory contains a refresh control circuit (3, 4, 7) and a memory circuit (2) for storing a plurality of register bits (2-1 to 2-n), a respective one of the register bits being assigned to at least one of the memory cells. In the event of an access to one of the memory cells, a set circuit (6) sets the assigned register bit (2-1 to 2-n), and a reset circuit (5) resets a set register bit (2-1 to 2-n). For controlling a refresh operation of one of the memory cells (MC), the refresh control circuit (3, 4, 7) evaluates the assigned register bit (2-1 to 2-n) and carries out the refresh operation in a manner dependent on the state of said register bit. For a refresh operation that is to be effected, a plurality of the memory cells (MC) are selected in an ascending or descending order of their addresses (x-Adr), and the respectively assigned register bits (2-1 to 2-n) of the memory cells, for resetting, are selected in an opposite order in a descending or ascending order of their addresses (x-Adr).

Claims

1. A circuit for refreshing memory cells of a dynamic memory, the circuit comprising:

a memory cell array including a plurality of dynamic random access memory cells;

a refresh control circuit coupled to the memory cell array so as to drive the memory cell array and access ones of the memory cells for a refresh operation, the refresh control circuit including a first selection circuit that selects at least one of the memory cells for a refresh operation that is to be effected;

a memory circuit for storing a plurality of register bits, a respective one of the register bits being assigned to at least one of the memory cells;

a set circuit coupled to the memory circuit so as to set the assigned register bit in the event of an access to one of the memory cells; and

a reset circuit coupled to the memory circuit so as to reset a set register bit, the reset circuit including a second selection circuit that defines which of the register bits is reset.

2. The circuit of claim 1 wherein

the refresh control circuit calls up the state of the register bits and accesses the memory cell array in such a way that the memory cell assigned to the respective register bit is refreshed in a manner dependent on the state of said register bit;

the first selection circuit selects a plurality of the memory cells in an ascending or descending order of their addresses; and

the second selection circuit selects the respectively assigned register bits of the memory cells in an opposite order in a descending or ascending order of their addresses.

3. The circuit as claimed in claim 2, wherein

a respective one of the register bits is assigned to one of a plurality of groups of memory cells of the dynamic memory, wherein each memory cell in the group of memory cells can be selected;

and

the refresh control circuit accesses the memory cell array in such a way that the memory cells of the group of memory cells assigned to the respective register bit are refreshed in a manner dependent on the state of the register bit.

4. The circuit as claimed in claim 2 wherein the first selection circuit selects, for a refresh operation that is to be effected, one of the memory cells whose assigned register bit is not set.

5. The circuit as claimed in claim 2 wherein the refresh control circuit evaluates the respectively assigned register bit and carries out a refresh operation of one of the memory cells in a manner dependent on the state of the evaluated register bit.

6. The circuit as claimed in claim 2 wherein the second selection circuit successively selects the respectively assigned register bits of a plurality of memory cells and resets the respective register bit in the process.

7. The circuit as claimed in claim 2 wherein the second selection circuit successively selects in a targeted manner the respectively assigned register bits of a plurality of memory cells which are set, and resets the respective register bit in the process.

8. The circuit as claimed in claim 2 wherein the refresh control circuit includes an oscillator that is coupled to the second selection circuit, for incrementing or decrementing an address stored in the second selection circuit with a defined first clock rate.

9. The circuit as claimed in claim 8 wherein the first clock rate of the oscillator can be set externally by means of a trimming signal.

10. The circuit as claimed in claim 2 wherein the refresh control circuit includes an oscillator that is coupled to the first selection circuit, for incrementing or decrementing an address stored in the first selection circuit with a defined second clock rate.

11. The circuit as claimed in claim 10 wherein the second clock rate of the oscillator can be set externally by means of a trimming signal.

12. The circuit as claimed in claim 10 and further comprising a temperature sensor circuit for detecting a temperature of the dynamic memory, the clock rate of the oscillator can be set by a control signal of the temperature sensor circuit in a manner dependent on the temperature of the dynamic memory.

13. The circuit as claimed in claim 1 and further comprising a supervisory unit coupled to receive each of the register bits, the supervisory unit outputting an AND combination of the register bits.

14. The circuit as claimed in claim 12 wherein the supervisory unit includes an output which, for the external read-out of the combination result, can be coupled to a circuit terminal that can be contact-connected externally.

15. The circuit as claimed in claim 12 wherein the supervisory unit includes an output which, for the external read-out of the combination result, can be coupled to a register circuit that can be read externally.

16. The circuit as claimed in claim 1 wherein the memory circuit comprises dynamic memory cells in which the register bits are stored, a positive charge being stored in the dynamic memory cells for the setting of the respective register bit.

17. A method for refreshing memory cells of a dynamic memory, the method comprising:

storing a plurality of register bits, a respective one of the register bits being assigned to at least one of the memory cells of the dynamic memory, which register bit is set in the event of an access to the assigned memory cell and is reset at a later point in time;

determining a memory cell that is to be refreshed;

evaluating the assigned register bit for the determined memory cell; and

performing a refresh operation on the determined memory cell if a state of the register bit indicates that a refresh operation is to be carried out, wherein the refresh operation is not performed if the state of the register bit indicates that a refresh operation is not to be carried out.

18. The method of claim 17 wherein performing a refresh operation comprises selecting a plurality of the memory cells in an ascending or descending order of their addresses.

19. The method of claim 18 and further comprising selecting the respectively assigned register bits of the memory cells for resetting, the selecting being performed in an order opposite of the order that the plurality of memory cells were selected.