System and method for automatically correcting duty cycle distortion
First Claim
1. A system for automatically correcting duty cycle distortion in a data input signal, comprising:
- a slicer operable to receive the data input signal and compare the data input signal with a slicer offset voltage to generate a sliced data signal, the slicer being further operable to receive an offset control signal to automatically adjust the slicer offset voltage;
a phase detector circuit operable to receive the sliced data signal and a recovered clock signal and to compare the sliced data signal with the recovered clock signal to generate a rising edge output signal and a falling edge output signal, the rising edge output signal corresponding to a phase difference between a rising edge of the sliced data signal and an edge of the recovered clock signal, the falling edge output signal corresponding to a phase difference between a falling edge of the sliced data signal and an edge of the recovered clock signal;
a first feedback circuit operable to phase-lock the recovered clock signal to the sliced data signal utilizing at least one of the rising edge output signal and the falling edge output signal; and
at least one of the rising edge output signal and the falling edge output signal being configured in a second feedback circuit to generate the offset control signal.
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Accused Products
Abstract
In accordance with the teachings described herein, systems and methods are provided for automatically correcting duty cycle distortion. A slicer may be used to receive a data input signal and compare the data input signal with a slicer offset voltage to generate a sliced data signal. The slicer may also receive an offset control signal to automatically adjust the slicer offset voltage. A phase detector may be used to receive the sliced data signal and a recovered clock signal and to compare the sliced data signal with the recovered clock signal to generate a rising edge output signal and a falling edge output signal. The rising edge output signal may correspond to a phase difference between a rising edge of the sliced data signal and an edge of the recovered clock signal. The falling edge output signal may correspond to a phase difference between a falling edge of the sliced data signal and an edge of the recovered clock signal. A first feedback circuit may be used to phase-lock the recovered clock signal to the sliced data signal utilizing at least one of the rising edge output signal and the falling edge output signal. At least one of the rising edge output signal and the falling edge output signal may be configured in a second feedback circuit to generate the offset control signal.
55 Citations
39 Claims
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1. A system for automatically correcting duty cycle distortion in a data input signal, comprising:
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a slicer operable to receive the data input signal and compare the data input signal with a slicer offset voltage to generate a sliced data signal, the slicer being further operable to receive an offset control signal to automatically adjust the slicer offset voltage;
a phase detector circuit operable to receive the sliced data signal and a recovered clock signal and to compare the sliced data signal with the recovered clock signal to generate a rising edge output signal and a falling edge output signal, the rising edge output signal corresponding to a phase difference between a rising edge of the sliced data signal and an edge of the recovered clock signal, the falling edge output signal corresponding to a phase difference between a falling edge of the sliced data signal and an edge of the recovered clock signal;
a first feedback circuit operable to phase-lock the recovered clock signal to the sliced data signal utilizing at least one of the rising edge output signal and the falling edge output signal; and
at least one of the rising edge output signal and the falling edge output signal being configured in a second feedback circuit to generate the offset control signal. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31)
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32. A method for automatically correcting duty cycle distortion in a data input signal, comprising:
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comparing the data input signal with a slicer offset voltage to generate a sliced data signal;
comparing the sliced data signal with a recovered clock signal to generate a rising edge output signal and a falling edge output signal, the rising edge output signal corresponding to a phase difference between a rising edge of the sliced data signal and an edge of the recovered clock signal, the falling edge output signal corresponding to a phase difference between a falling edge of the sliced data signal and an edge of the recovered clock signal;
synchronizing the recovered clock signal with at least one of the rising edge output signal and the falling edge output signal; and
automatically adjusting the slicer offset voltage as a function of at least one of the rising edge output signal and the falling edge output signal to correct for duty cycle distortion in the data input signal. - View Dependent Claims (33)
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34. A clock and data recovery system, comprising:
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means for receiving a data input signal and comparing the data input signal with an offset voltage to generate a sliced data signal, means for comparing the sliced data signal with a recovered clock signal to generate a rising edge output signal and a falling edge output signal, the rising edge output signal corresponding to a phase difference between a rising edge of the sliced data signal and an edge of the recovered clock signal, the falling edge output signal corresponding to a phase difference between a falling edge of the sliced data signal and an edge of the recovered clock signal;
means for synchronizing the sliced data signal with the recovered clock signal to generate a retimed data signal;
a feedback circuit being operable to phase-lock the recovered clock signal to the sliced data signal utilizing at least one of the rising edge output signal and the falling edge output signal; and
means for automatically adjusting the offset voltage as a function of at least one of the rising edge output signal and the falling edge output signal to correct for duty cycle distortion in the data input signal.
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35. A system for automatically correcting duty cycle distortion in a data input signal, comprising:
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a slicer operable to receive the data input signal and compare the data input signal with a slicer offset voltage to generate a sliced data signal, the slicer being further operable to receive an offset control signal to automatically adjust the slicer offset voltage;
one or more phase detector circuits operable to receive the sliced data signal and a recovered clock signal and to compare the sliced data signal with the recovered clock signal to generate one or more phase detector output signals corresponding to a phase difference between the sliced data signal and the recovered clock signal;
a first feedback circuit operable to phase-lock the recovered clock signal to the sliced data signal utilizing at least one phase detector output signal; and
at least one phase detector output signal being configured in a second feedback circuit to generate the offset control signal.
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36. A system for automatically correcting duty cycle distortion in a data input signal, comprising:
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a slicer operable to receive the data input signal and compare the data input signal with a slicer offset signal to generate a sliced data signal, the slicer being further operable to receive an offset control signal to automatically adjust the slicer offset signal;
a first circuit operable to phase lock the sliced data signal with a recovered clock signal; and
a second circuit operable to generate the offset control signal by comparing a pulse width of the sliced data signal with a clock period of the recovered clock signal. - View Dependent Claims (37, 38, 39)
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Specification