Vertical gain cell

• US 20050032313A1
• Filed: 08/31/2004
• Published: 02/10/2005
• Est. Priority Date: 03/04/2003
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Forbes, Leonard
• Granted Patent: US 7,241,658 B2
• Time in Patent Office: Days
• US Class Current: 438/270
• CPC Class Codes: H01L 27/0705 comprising components of the field effect type
• CPC Class Codes: H01L 29/7841 with floating body, e.g. programmable transistors
• CPC Class Codes: H10B 12/00 Dynamic random access memory [DRAM] devices
• CPC Class Codes: H10B 12/20 DRAM devices comprising floating-body transistors, e.g. floating-body cells
• CPC Class Codes: H10B 12/395 the transistor being vertical

Abstract

A high density vertical gain cell is realized for memory operation. The gain cell includes a vertical MOS transistor used as a sense transistor having a floating body between a drain region and a source region, and a second vertical MOS transistor merged with the sense transistor. Addressing the second vertical MOS transistor provides a means for changing a potential of the floating body of the sense transistor. The vertical gain cell can be used in a memory array with a read data/bit line and a read data word line coupled to the sense transistor, and with a write data/bit line and a write data word line coupled to the second transistor of the vertical gain cell.

Claims

1. A method of forming an electronic device having a vertical gain cell comprising:

forming a first vertical MOS transistor having a floating body; and

forming a second vertical MOS transistor merged with the first vertical MOS transistor, and

coupling the second vertical MOS transistor to a conductive line such that addressing the second vertical MOS transistor couples the floating body to the conductive line.

2. The method of claim 1, wherein the method further includes forming a drain region for the second vertical MOS transistor merged with at least a portion of the floating body of the first vertical MOS transistor.

3. The method of claim 2, wherein the method further includes forming a body region for the second vertical MOS transistor merged with at least a portion of a source region of the first vertical MOS transistor.

4. The method of claim 3, wherein the method further includes forming a heavily doped source line coupled to the source region of the first vertical MOS transistor.

5. The method of claim 1, wherein the method further includes forming a write data word line coupled to a gate of the second vertical MOS transistor.

6. The method of claim 1, wherein the method further includes forming a read data/bit line coupled to a drain region of the first vertical MOS transistor.

7. The method of claim 1, wherein the method further includes forming a read data word line coupled to a gate of the first vertical MOS transistor.

8. The method of claim 1, wherein the method further includes forming the vertical gain cell on a p-type substrate.

9. The method of claim 1, wherein forming the first vertical MOS transistor includes forming a p-channel MOS (PMOS) transistor.

10. The method of claim 1, wherein forming the second vertical MOS transistor includes forming an n-channel MOS (NMOS) transistor.

11. The method of claim 1, wherein the method further includes forming the vertical gain cell on an n-type substrate or a SOI substrate.

12. The method of claim 1, wherein forming the first vertical MOS transistor includes forming an n-channel MOS (NMOS).

13. The method of claim 1, wherein forming the second vertical MOS transistor includes forming a p-channel MOS (PMOS) transistor.

14. The method of claim 1, wherein forming a second vertical MOS transistor merged with the first vertical MOS transistor includes forming the vertical gain cell with an area of approximately 4F², where F is a minimum feature size.

15. The method of claim 1, wherein forming the electronic device having a vertical gain cell includes forming the electronic device having a vertical gain cell in a memory.

16. The method of claim 1, wherein forming the electronic device having a vertical gain cell includes forming the electronic device having a vertical gain cell in an electronic apparatus.

17. A method of forming a memory comprising:

forming a number of read data word lines;

forming a number of write data word lines;

forming a number of write data/bit lines; and

forming a number of vertical gain memory cells, each vertical memory cell coupled to one of the number of read data word lines and one of the write data word lines, wherein forming each vertical gain memory cell includes;

forming a first vertical MOS transistor having a floating body; and

forming a second vertical MOS transistor merged with the first vertical MOS transistor, and

coupling the second vertical MOS transistor to a write data/bit line such that addressing the second vertical MOS transistor operatively couples the floating body to the write data/bit line.

18. The method of claim 17, wherein the method further includes forming a drain region for the second vertical MOS transistor merged with at least a portion of the floating body of the first vertical MOS transistor.

19. The method of claim 17, wherein the method further includes forming a body region for the second vertical MOS transistor merged with at least a portion of a source region of the first vertical MOS transistor.

20. The method of claim 17, wherein the method further includes:

forming a number of read data/bit lines;

coupling a read data/bit line to a drain region of the first vertical MOS transistor; and

coupling a source line to a source region of the first vertical MOS transistor.

21. The method of claim 17, wherein forming each vertical gain memory cell further includes forming the second vertical MOS transistor merged with the first vertical MOS transistor configured as a vertical gain memory cell having an area of approximately 4F², where F is a minimum feature size.

22. The method of claim 17, wherein forming each vertical gain memory cell further includes forming the vertical gain memory cell on a p-type substrate and forming the first vertical MOS transistor as a p-channel MOS (PMOS) transistor.

23. The method of claim 17, wherein forming each vertical gain memory cell further includes forming the vertical gain memory cell on an n-type substrate or a SOI substrate and forming the first vertical MOS transistor as an n-channel MOS (NMOS).

24. The method of claim 17, wherein coupling the second vertical MOS transistor to a write data/bit line includes forming the second MOS transistor disposed on the write data/bit line.

25. The method of claim 24, wherein forming a number of read data/bit lines includes forming metallic read data/bit lines and forming a number of write data/bit lines includes forming a heavily doped n-type layer on a p-type substrate.

26. The method of claim 17, wherein the method further includes forming a heavily doped p-type polysilicon source line, wherein forming the number of read data word lines and the number of write data word lines includes forming polysilicon read data word lines and polysilicon write data word lines.

27. A method of forming an electronic apparatus comprising:

providing a processor; and

coupling the processor to a memory, the memory formed by a method including;

forming a number of read data word lines;

forming a number of write data word lines;

forming a number of write data/bit lines; and

forming a number of vertical gain memory cells, each vertical memory cell coupled to one of the number of read data word lines and one of the write data word lines, wherein forming each vertical gain memory cell includes;

forming a first vertical MOS transistor having a floating body; and

forming a second vertical MOS transistor merged with the first vertical MOS transistor, and

coupling the second vertical MOS transistor to a write data/bit line such that addressing the second vertical MOS transistor operatively couples the floating body to the write data/bit line.

28. The method of claim 27, wherein the method further includes forming a drain region for the second vertical MOS transistor merged with at least a portion of the floating body of the first vertical MOS transistor.

29. The method of claim 28, wherein the method further includes forming a body region for the second vertical MOS transistor merged with at least a portion of a source region of the first vertical MOS transistor.

30. The method of claim 27, wherein the method further includes:

forming a number of read data/bit lines;

coupling a read data/bit line to a drain region of the first vertical MOS transistor; and

coupling a source line to a source region of the first vertical MOS transistor.

31. The method of claim 27, wherein forming each vertical gain memory cell further includes forming the vertical gain memory cell having an area of approximately 4F², where F is a minimum feature size.

32. The method of claim 27, wherein each vertical gain memory cell further includes forming the vertical gain memory cell on a p-type substrate and forming the first vertical MOS transistor as a p-channel MOS (PMOS) transistor.

33. The method of claim 27, forming each vertical gain memory cell further includes forming the vertical gain memory cell on an n-type substrate or a SOI substrate and forming the first vertical MOS transistor as an n-channel MOS (NMOS).