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Method for reducing defects in post passivation interconnect process

  • US 20050032353A1
  • Filed: 08/06/2003
  • Published: 02/10/2005
  • Est. Priority Date: 08/06/2003
  • Status: Active Grant
First Claim
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1. A method of forming post passivation interconnects for an integrated circuit having a plurality of contact regions, the method comprising:

  • forming a passivation layer over the integrated circuit, the passivation layer, formed from a non-oxide material;

    forming a buffer layer over the passivation layer, the buffer layer comprising a silicon oxide layer;

    removing a top portion of the buffer layer;

    depositing a post passivation metal layer over the buffer layer after removing a top portion of the buffer layer; and

    forming a connection pattern in the post passivation metal layer such that portions of the connection pattern are electrically coupled to the contact regions.

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