Method for reducing defects in post passivation interconnect process

• US 20050032353A1
• Filed: 08/06/2003
• Published: 02/10/2005
• Est. Priority Date: 08/06/2003
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Wang, Ying-Lang, Cheng, Hsi-Kuei, Su, Chin-Hao, Chen, Chu-Chang, Feng, Hsien-Ping, Chien, Hung-Ju, Chan, Hsun-Chang, Chang, Shih-Tzung
• Granted Patent: US 7,026,233 B2
• Time in Patent Office: Days
• US Class Current: 438/624
• CPC Class Codes: H01L 2224/02 Bonding areas; Manufacturing methods related thereto
• CPC Class Codes: H01L 2224/0231 Manufacturing methods of the redistribution layers
• CPC Class Codes: H01L 2224/02377 Fan-in arrangement
• CPC Class Codes: H01L 2224/05001 Internal layers
• CPC Class Codes: H01L 2224/05022 the internal layer being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/05124 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05567 the external layer being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/05624 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05647 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/0615 Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry
• CPC Class Codes: H01L 2224/0616 Random array, i.e. array with no symmetry
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 23/3114 the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 24/02 Bonding areas on insulating substrates, e.g. chip carriers, H01L23/49816, H01L23/49838, H01L23/5389; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 24/11 Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 of an individual bump connector
• CPC Class Codes: H01L 2924/0001 : Technical content checked by a classifier
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01018 : Argon [Ar]
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01032 : Germanium [Ge]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01075 : Rhenium [Re]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/18161 : of a flip chip

Abstract

A method of forming post passivation interconnects for an integrated circuit is disclosed. A passivation layer of a non-oxide material is formed over the integrated circuit. A buffer layer is then formed over the passivation layer. The buffer layer preferably is a silicon oxide layer with a thickness substantially smaller than a thickness of the passivation layer. A post passivation metal layer is deposited over the buffer layer and a connection pattern is formed in the post passivation metal layer.

Claims

1. A method of forming post passivation interconnects for an integrated circuit having a plurality of contact regions, the method comprising:

forming a passivation layer over the integrated circuit, the passivation layer, formed from a non-oxide material;

forming a buffer layer over the passivation layer, the buffer layer comprising a silicon oxide layer;

removing a top portion of the buffer layer;

depositing a post passivation metal layer over the buffer layer after removing a top portion of the buffer layer; and

forming a connection pattern in the post passivation metal layer such that portions of the connection pattern are electrically coupled to the contact regions.

2. The method of claim 1 wherein the top portion of the buffer layer is removed in a cleaning chamber having an inner wall comprising primarily quartz.

3. The method of claim 2 wherein the cleaning chamber is in a vacuum condition during the removing step and wherein the post passivation metal layer is deposited over the buffer layer after the removing step without breaking the vacuum condition in the cleaning chamber.

4. The method of claim 1 wherein passivation layer is formed in a first chamber that is in a vacuum condition and wherein the buffer layer is formed over the passivation layer in the first chamber and without breaking the vacuum condition in the first chamber after forming the passivation layer.

5. The method of claim 4 wherein the top portion of the buffer layer is removed in the first chamber, the method further comprising breaking a vacuum condition in the first chamber before the step of etching the buffer layer.

6. The method of claim 1 wherein the passivation layer comprises a layer of silicon nitride.

7. The method of claim 1 wherein the passivation layer comprises more than one layer and wherein an uppermost layer comprises silicon nitride.

8. The method of claim 1 wherein the buffer layer has a thickness substantially smaller than a thickness of the passivation layer and wherein the buffer layer has a thickness less than about 25 nanometers.

9. The method of claim 1 wherein the buffer layer has a thickness substantially smaller than a thickness of the passivation layer and wherein the ratio of the thickness of the passivation layer to the thickness of the buffer layer is greater than about 20.

10. A method of depositing a conductive layer over an integrated circuit, the method comprising:

providing a substantially completed integrated circuit, the substantially completed integrated circuit including a silicon nitride passivation layer at an uppermost surface;

forming an oxide buffer layer over and abutting the silicon nitride passivation layer, the oxide buffer layer having a thickness substantially smaller than a thickness of the passivation layer;

forming a metal layer over and abutting the oxide buffer layer, and

patterning the metal layer.

11. The method of claim 10 wherein the oxide buffer layer is etched in a chamber that includes quartz inner walls.

12. The method of claim 10 wherein the thickness of the silicon nitride passivation layer is at least about 20 times greater than the thickness of the oxide buffer layer.

13. The method of claim 12 wherein the oxide buffer layer has a thickness of less than about 25 nm.

14-21. -21. Canceled.

22. A method of forming a semiconductor device, the method comprising:

providing a silicon substrate having a plurality of active devices formed therein, the active devices being interconnected by a plurality of metal layers including an uppermost metal layer, the uppermost metal layer including a plurality of contact regions;

forming a nitride passivation layer overlying the uppermost metal layer except for a portion of the contact regions;

forming an oxide buffer layer overlying the nitride passivation layer, the oxide buffer layer having a thickness substantially smaller than a thickness of the nitride passivation layer; and

forming a post passivation metal layer overlying the oxide buffer layer, the post passivation metal layer patterned so as to electrically couple the plurality of contact regions to a plurality of contact pads formed in the post passivation metal layer.

23. The method of claim 22 wherein forming a nitride passivation layer comprises forming a silicon nitride layer and wherein forming an oxide buffer layer comprises forming a silicon oxide layer.

24. The method of claim 22 wherein forming an oxide buffer layer comprises forming an oxide buffer layer with a thickness of less than 25 nanometers.

25. The method of claim 22 wherein thickness of the nitride passivation layer is at least about 20 times greater than the thickness of the oxide buffer layer.

26. The method of claim 22 wherein the uppermost metal layer includes a plurality of contact regions disposed around the periphery of the chip and the contact pads are arranged over a central portion of the semiconductor chip.

27. The method of claim 22 and further comprising:

providing a package substrate having a plurality of contact pads arranged in a configuration corresponding to the contact pads on the semiconductor chip; and

attaching the contact pads of the package substrate to the contact pads on the semiconductor chip via a plurality of solder bumps, wherein the solder bumps electrically couple the contact pads on the semiconductor chip with the contact pads on the package substrate.

28. The method of claim 22 wherein the uppermost metal layer comprises a layer of copper.

29. A method of forming a post passivation metal layer over an integrated circuit, the method comprising:

providing a substantially completed integrated circuit, the substantially completed integrated circuit including a silicon nitride passivation layer at an uppermost surface;

forming an oxide buffer layer over and physically contacting the silicon nitride passivation layer, the oxide buffer layer having a thickness substantially smaller than a thickness of the passivation layer;

removing a top portion of the oxide buffer layer, the top portion of the buffer layer being removed in a cleaning chamber having an inner wall comprising primarily quartz, the cleaning chamber being held in a vacuum condition during the removing;

depositing a metal layer over and physically contacting the oxide buffer layer, wherein the metal layer is deposited after the removing step without breaking the vacuum condition in the cleaning chamber; and

patterning the metal layer.

30. The method of claim 29 wherein the passivation layer comprises a layer of Si₃N₄.

31. The method of claim 29 wherein the passivation layer comprises more than one layer and wherein an uppermost layer comprises silicon nitride.

32. The method of claim 29 wherein forming an oxide buffer layer comprises forming buffer layer that has a thickness of less than about 25 nanometers.

33. The method of claim 29 wherein the ratio of the thickness of the passivation layer to the thickness of the buffer layer is greater than about 20.