Receiver, transceiver circuit, signal transmission method, and signal transmission system

• US 20050033902A1
• Filed: 09/01/2004
• Published: 02/10/2005
• Est. Priority Date: 07/14/1999
• Status: Active Grant

• Current Assignee: Fujitsu Limited
• Original Assignee: Fujitsu Limited
• Inventors: Tamura, Hirotaka
• Granted Patent: US 7,389,097 B2
• Time in Patent Office: Days
• US Class Current: 711/2
• CPC Class Codes: H03F 3/45183 Long tailed pairs H03F3/4521, H03F3/45237 take precedence
• CPC Class Codes: H03F 3/45475 using IC blocks as the active amplifying circuit
• CPC Class Codes: H03F 3/45762 using switching means, e.g. sample and hold
• CPC Class Codes: H03F 3/45986 using switching means, e.g. sample and hold
• CPC Class Codes: H04L 25/0274 Arrangements for ensuring balanced coupling
• CPC Class Codes: H04L 25/0292 Arrangements specific to the receiver end
• CPC Class Codes: H04L 25/061 providing hard decisions only; arrangements for tracking or suppressing unwanted low frequency components, e.g. removal of dc offset removal of dc offset in coupling arrangements H04L25/029, H04L25/0296
• CPC Class Codes: H04L 5/14 Two-way operation using the same type of signal, i.e. duplex
• CPC Class Codes: H04L 5/1461 Suppression of signals in the return path, i.e. bidirectional control circuits
• CPC Class Codes: H04L 7/033 using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop

Abstract

A receiver has an offset application circuit for applying a known offset to an input signal, and a decision circuit for comparing the offset-applied input signal with a reference voltage. The level of the input signal is determined based on the known offset and on the result output from the decision circuit. With this configuration, a large common mode voltage can be eliminated in a circuit used for signal transmission.

Claims

1. A receiver comprising:

an offset application circuit for applying a known offset to an input signal; and

a decision circuit for comparing said offset-applied input signal with a reference voltage, wherein the level of said input signal is determined based on said known offset and on a result output from said decision circuit.

2. The receiver as claimed in claim 1, wherein said offset application circuit includes an offset level control circuit for controlling the level of said offset by a digital signal.

3. The receiver as claimed in claim 2, further comprising:

an input signal level detection circuit for detecting the level of said input signal by increasing or decreasing the level of said offset using said offset level control circuit, and by finding an offset level where the result output from said decision circuit changes.

4. The receiver as claimed in claim 3, further comprising:

a timing control circuit for controlling decision timing in said decision circuit in such a manner as to vary said decision timing relative to an internal clock in said receiver, and wherein the level of said offset is adjusted by judging an externally supplied, predetermined test pattern at output timing of said timing control circuit, and information concerning said input signal is acquired using said input signal level detection circuit.

5. The receiver as claimed in claim 1, wherein said offset voltage application circuit passes a constant current to a termination resistor provided in parallel to an input terminal of said receiver.

6. The receiver as claimed in claim 1, wherein said offset voltage application circuit includes a plurality of capacitors and switches, and varies the level of said offset by varying a precharge voltage of each of said capacitors.

7. The receiver as claimed in claim 1, wherein said offset voltage application circuit varies the level of said offset by passing a constant current into an internal node in said receiver.

8. The receiver as claimed in claim 1, wherein said offset voltage application circuit varies the level of said offset by passing a constant current into an internal node in said receiver.

9. The receiver as claimed in claim 1, wherein received signal quality of said input signal is diagnosed, or a characteristic of said receiver or driver is adjusted, by using the waveform of said input signal obtained from said known offset and the result output from said decision circuit.

10. A transceiver circuit having a receiver for receiving a signal input thereto, and a driver for outputting a signal, wherein said receiver comprises:

an offset application circuit for applying a known offset to said input signal; and

a decision circuit for comparing said offset-applied input signal with a reference voltage, wherein the level of said input signal is determined based on said known offset and on a result output from said decision circuit.

11. The transceiver circuit as claimed in claim 10, wherein said offset application circuit includes an offset level control circuit for controlling the level of said offset by a digital signal.

12. The transceiver circuit as claimed in claim 11, wherein said receiver further comprises:

an input signal level detection circuit for detecting the level of said input signal by increasing or decreasing the level of said offset using said offset level control circuit, and by finding an offset level where the result output from said decision circuit changes.

13. The transceiver circuit as claimed in claim 12, wherein said receiver further comprises:

a timing control circuit for controlling decision timing in said decision circuit in such a manner as to vary said decision timing relative to an internal clock in said receiver, wherein the level of said offset is adjusted by judging an externally supplied, predetermined test pattern at an output timing of said timing control circuit, and information concerning said input signal is acquired using said input signal level detection circuit.

14. The transceiver circuit as claimed in claim 10, wherein said offset voltage application circuit passes a constant current to a termination resistor provided in parallel to an input terminal of said receiver.

15. The transceiver circuit as claimed in claim 10, wherein said offset voltage application circuit includes a plurality of capacitors and switches, and varies the level of said offset by varying a precharge voltage of each of said capacitors.

16. The transceiver circuit as claimed in claim 10, wherein said offset voltage application circuit varies the level of said offset by passing a constant current into an internal node in said receiver.

17. The transceiver circuit as claimed in claim 10, wherein said offset voltage application circuit varies the level of said offset by passing a constant current into an internal node in said receiver.

18. The transceiver circuit as claimed in claim 10, wherein received signal quality of said input signal is diagnosed, or a characteristic of said receiver or driver is adjusted, by using the waveform of said input signal obtained from said known offset and the result output from said decision circuit.

19. The transceiver circuit as claimed in claim 10, further comprising:

a test pattern transmitting circuit for transmitting a predetermined test pattern from said driver to a receiver in another transceiver circuit;

a test pattern judging circuit for receiving, by said receiver, a test pattern transmitted from a driver in another transceiver circuit and for judging said received test pattern at a predetermined timing using said decision circuit; and

a test pattern level detection circuit for detecting the level of said test pattern by adjusting the level of said offset, and wherein an equalization parameter of said receiver is adjusted using an output of said test pattern level detection circuit.

20. The transceiver circuit as claimed in claim 10, further comprising:

a boundary signal transmitting circuit for transmitting from said driver to a receiver in another transceiver circuit a boundary signal which should be judged to be at a boundary between data “

0” and

“

1”

; and

a boundary offset seeking circuit for receiving, by said receiver, a boundary signal transmitted from a driver in another transceiver circuit and for seeking such a boundary offset that the result of a decision in said decision circuit agrees with the boundary between data “

0” and

“

1”

, and wherein zero adjustment of said receiver is performed by applying said boundary offset to said receiver at the time of usual input signal reception.

21. The transceiver circuit as claimed in claim 10, further comprising:

a test pattern transmitting circuit for transmitting a predetermined test pattern from said driver to a receiver in another transceiver circuit;

a receive timing changing test pattern level detection circuit for receiving, by said receiver, a test pattern transmitted from a driver in another transceiver circuit by sequentially changing a receive timing in said receiver and for detecting the level of said test pattern; and

an operation circuit for adjusting a parameter of said transceiver circuit by using an output of said receive timing changing test pattern level detection circuit.

22. A signal transmission system having a first transceiver circuit, a second transceiver circuit, and a signal transmission line connecting between said first and second transceiver circuits, wherein:

each of said transceiver circuits comprises a receiver for receiving a signal input thereto, and a driver for outputting a signal; and

said receiver includes an offset application circuit for applying a known offset to said input signal and a decision circuit for comparing said offset-applied input signal with a reference voltage, wherein the level of said input signal is determined based on said known offset and on a result output from said decision circuit.

23. The signal transmission system as claimed in claim 22, wherein said offset application circuit includes an offset level control circuit for controlling the level of said offset by a digital signal.

24. The signal transmission system as claimed in claim 22, wherein said receiver further includes:

an input signal level detection circuit for detecting the level of said input signal by increasing or decreasing the level of said offset using said offset level control circuit, and by finding an offset level where the result output from said decision circuit changes.

25. The signal transmission system as claimed in claim 24, wherein said receiver further includes:

a timing control circuit for controlling decision timing in said decision circuit in such a manner as to vary said decision timing relative to an internal clock in said receiver, wherein the level of said offset is adjusted by judging an externally supplied, predetermined test pattern at output timing of said timing control circuit, and information concerning said input signal is acquired using said input signal level detection circuit.

26. The signal transmission system as claimed in claim 22, wherein said offset voltage application circuit passes a constant current to a termination resistor provided in parallel to an input terminal of said receiver.

27. The signal transmission system as claimed in claim 22, wherein said offset voltage application circuit includes a plurality of capacitors and switches, and varies the level of said offset by varying a precharge voltage of each of said capacitors.

28. The signal transmission system as claimed in claim 22, wherein said offset voltage application circuit varies the level of said offset by passing a constant current into an internal node in said receiver.

29. The signal transmission system as claimed in claim 22, wherein said offset voltage application circuit varies the level of said offset by passing a constant current into an internal node in said receiver.

30. The signal transmission system as claimed in claim 22, wherein received signal quality of said input signal is diagnosed, or a characteristic of said receiver or driver is adjusted, by using the waveform of said input signal obtained from said known offset and the result output from said decision circuit.

31. The signal transmission system as claimed in claim 22, wherein:

a predetermined test pattern is transmitted from said driver in said first transceiver circuit, said test pattern is judged at predetermined timing using said receiver in said second transceiver circuit; and

the level of said test pattern is detected by adjusting the level of said offset in said second transceiver circuit, thereby adjusting an equalization parameter of said receiver in said second transceiver circuit.

32. The signal transmission system as claimed in claim 22, wherein:

a boundary signal which should be judged to be at a boundary between data “

0” and

“

1”

is transmitted to said receiver in said second transceiver circuit by said driver in said first transceiver circuit;

said boundary signal is received by said receiver in said second transceiver circuit and such a boundary offset is sought so that the result of a decision in said decision circuit of said receiver agrees with the boundary between data “

0” and

“

1”

; and

zero adjustment of said receiver in said second transceiver circuit is performed by applying said boundary offset to said receiver at the time of usual input signal reception.

33. The signal transmission system as claimed in claim 22, wherein:

a predetermined test pattern is transmitted to said receiver in said first transceiver circuit by said driver in said first transceiver circuit; and

said test pattern is received by said receiver in said second transceiver circuit by sequentially changing the receive timing in said receiver and the level of said test pattern is detected, thereby adjusting a parameter of said second transceiver circuit.

34. A receiver having a plurality of signal lines and a capacitor network having capacitors connected to said signal lines and switches for controlling the connection of said capacitors, wherein:

said receiver includes a common mode voltage elimination circuit for eliminating a common mode voltage present on said plurality of signal lines by connecting at least one of the capacitor nodes containing the component of said common mode voltage to a node held to a specific voltage value.

35. The receiver as claimed in claim 34, wherein said common mode voltage elimination circuit includes a corresponding voltage generating circuit for generating a voltage value corresponding to said common mode voltage, and a capacitor charging circuit for charging one end of said capacitor by the output voltage of said corresponding voltage generating circuit.

36. The receiver as claimed in claim 34, wherein said common mode voltage elimination circuit includes a difference voltage capacitor charging circuit for charging an input capacitor by a difference voltage appearing on said plurality of signal lines, and a connection control circuit for connecting a terminal of said input capacitor to an input terminal of a decision circuit subsequently to a charge period.

37. The receiver as claimed in claim 36, wherein said difference voltage capacitor charging circuit performs the elimination of said common mode voltage simultaneously with a differential to single-ended conversion by connecting one node of said capacitor to a constant voltage.

38. The receiver as claimed in claim 36, wherein said difference voltage capacitor charging circuit couples two nodes of said capacitor respectively to single-ended amplifiers.

39. The receiver as claimed in claim 34, wherein said capacitor network implements PRD.

40. The receiver as claimed in claim 34, wherein said receiver applies feedback for the elimination of said common mode voltage to outputs of two single-ended amplifiers to which signals from said capacitor network are input.

41. The receiver as claimed in claim 34, wherein said capacitor network includes two or more coupling capacitors, and said coupling capacitors are connected in parallel during a precharge period and in series during a decision period.

42. A receiver comprising a plurality of signal lines and a capacitor network having capacitors connected to said signal lines and switches for controlling the connection of said capacitors, wherein

said receiver includes a common mode voltage elimination circuit for eliminating a common mode voltage present on said plurality of signal lines by connecting at least one of capacitor nodes containing the component of said common mode voltage to a node precharged to a specific voltage value.

43. The receiver as claimed in claim 42, wherein said common mode voltage elimination circuit includes a corresponding voltage generating circuit for generating a voltage value corresponding to said common mode voltage, and a capacitor charging circuit for charging one end of said capacitor by the output voltage of said corresponding voltage generating circuit.

44. The receiver as claimed in claim 42, wherein said common mode voltage elimination circuit includes a difference voltage capacitor charging circuit for charging an input capacitor by a difference voltage appearing on said plurality of signal lines, and a connection control circuit for connecting a terminal of said input capacitor to an input terminal of a decision circuit subsequently to a charge period.

45. The receiver as claimed in claim 44, wherein said difference voltage capacitor charging circuit performs the elimination of said common mode voltage simultaneously with a differential to single-ended conversion by connecting one node of said capacitor to a constant voltage.

46. The receiver as claimed in claim 44, wherein said difference voltage capacitor charging circuit couples two nodes of said capacitor respectively to single-ended amplifiers.

47. The receiver as claimed in claim 42, wherein said capacitor network implements PRD.

48. The receiver as claimed in claim 42, wherein said receiver applies feedback for the elimination of said common mode voltage to outputs of two single-ended amplifiers to which signals from said capacitor network are input.

49. The receiver as claimed in claim 42, wherein said capacitor network includes two or more coupling capacitors, and said coupling capacitors are connected in parallel during a precharge period and in series during a decision period.

50. A receiver comprising:

an input line via which an input signal is supplied;

a plurality of sample-and-hold circuits for sequentially latching said input signal by a multi-phase periodic clock, and for holding said latched input signal; and

a decision circuit for making a decision on said input signal by generating a signal corresponding to a weighted sum of the outputs of said sample-and-hold circuits, wherein;

an output valid period of each sample-and-hold circuit is made longer than one bit time of said input signal; and

said decision circuit is operated by using the weighted sum generated during a period where the output valid period of said sample-and-hold circuit overlaps the output valid period of another sample-and-hold circuit operating before or after said sample-and-hold circuit.

51. The receiver as claimed in claim 50, wherein said decision circuit generates a voltage, current, or charge signal corresponding to the weighted sum of the outputs of said sample-and-hold circuits.

52. The receiver as claimed in claim 50, wherein:

an operating cycle of said sample-and-hold circuit is set equal to two bit times of said input signal; and

a sample period of said sample-and-hold circuit is made longer than a hold period thereof, thereby making the output valid period of said sample-and-hold circuit overlap into the output valid period of another sample-and-hold circuit operating before or after said sample-and-hold circuit.

53. The receiver as claimed in claim 50, wherein an operating cycle of said sample-and-hold circuit is set equal to three or more bit times of said input signal, and the output valid period of said sample-and-hold circuit is set equal to or longer than one bit time of said input signal.

54. The receiver as claimed in claim 50, wherein the weighted sum of the outputs of said sample-and-hold circuits is generated by converting the output signals of said sample-and-hold circuits into currents by a transconductor using transistors, and by passing said currents into a common load device.

55. The receiver as claimed in claim 54, wherein a weight in said weighted sum is adjusted by varying the number of transistors to be connected in parallel in said transconductor.

56. The receiver as claimed in claim 54, wherein a weight in said weighted sum is adjusted by varying a current bias value in said transconductor.

57. The receiver as claimed in claim 50, wherein said decision circuit generates the signal corresponding to the weighted sum of the outputs of said sample-and-hold circuits by interconnecting capacitors each charged to a hold voltage.

58. The receiver as claimed in claim 57, wherein said decision circuit generates said weighted sum based on differences in charges stored in said capacitors.

59. The receiver as claimed in claim 50, wherein said decision circuit generates the signal corresponding to the weighted sum of the outputs of said sample-and-hold circuits by moving charges corresponding to the outputs of said sample-and-hold circuits into a common capacitor through a charge transfer circuit.

60. The receiver as claimed in claim 59, wherein a weight in said weighted sum is adjusted by varying the number of transistors to be connected in parallel in said charge transfer circuit.

61. A transceiver circuit comprising:

a driver for outputting a transmit signal onto a signal transmission line;

a receiver for receiving a receive signal from said signal transmission line; and

a compensation voltage generating circuit for generating a compensation voltage used to compensate for an interference voltage caused by said driver, and for supplying said compensation voltage to said receiver, wherein bidirectional signal transmission is performed by controlling an output level of said compensation voltage generating circuit in accordance with the phase relationship between said transmit signal and said receive signal.

62. The transceiver circuit as claimed in claim 61, wherein said driver is a constant-current driver.

63. The transceiver circuit as claimed in claim 62, wherein said driver includes:

a first driver unit array having a plurality constant-current driver units; and

a second driver unit array having a plurality constant-current driver units, transmit signals being sequentially output by switching between said first and second driver unit arrays.

64. The transceiver circuit as claimed in claim 63, wherein each of said driver unit arrays controls the operating condition of said plurality of constant-current driver units in said each driver unit array and thereby adjusts a transient characteristic of said transmit signal.

65. The transceiver circuit as claimed in claim 64, further comprising:

a predriver for driving each of said driver unit arrays, wherein said predriver is driven by a 4n-phase clock whose cycle is twice as long as bit time T, where n denotes the number of driver units in said each driver unit array.

66. The transceiver circuit as claimed in claim 61, wherein said compensation voltage generating circuit is a replica driver having the same circuit configuration as that of said driver and is driven by the same data as that for said driver, and includes a unit for controlling the output amplitude and transient time of said replica driver.

67. The transceiver circuit as claimed in claim 66, wherein said driver comprises a plurality of driver units, and said replica driver is similar in configuration to one of said driver units constituting said driver.

68. The transceiver circuit as claimed in claim 67, wherein said compensation voltage generating circuit further includes:

a correction circuit for generating, based on a past output bit, a correction signal for improving the accuracy of said compensation voltage at decision timing in said receiver.

69. The transceiver circuit as claimed in claim 61, wherein said compensation voltage generating circuit generates said compensation voltage based on a data sequence consisting of the present bit and past bit of said transmit signal output from said driver and in accordance with the phase relationship between said transmit signal and said receive signal.

70. The transceiver circuit as claimed in claim 69, further comprising:

a unit for determining prior to actual signal transmission a compensation voltage for a boundary across which a decision in said receiver changes from data “

0”

to data “

1”

or from data “

1”

to data “

0”

, by transmitting a test pattern from the driver at one end while setting an output current level at zero in the driver at the other end; and

a unit for storing said determined compensation voltage, and wherein actual signal transmission is performed using said stored compensation voltage.

71. The transceiver circuit as claimed in claim 61, wherein said compensation voltage generating circuit includes:

a plurality of compensation voltage correction circuits each for generating a voltage level that depends on a data sequence consisting of the present bit and past bit of said transmit signal output from said driver and on the phase difference between said transmit signal and said receive signal; and

a selection circuit for selecting the output of one of said plurality of compensation voltage correction circuits in accordance with said data sequence.

72. The transceiver circuit as claimed in claim 71, further comprising:

a unit for determining prior to actual signal transmission a compensation voltage for a boundary across which a decision in said receiver changes from data “

0”

to data “

1”

or from data “

1”

to data “

1”

, by transmitting a test pattern from the driver at one end while setting an output current level at zero in the driver at the other end; and

a unit for storing said determined compensation voltage, and wherein actual signal transmission is performed using said stored compensation voltage.

73. The transceiver circuit as claimed in claim 61, wherein a compensation offset value is determined based on the value of a bit sequence of n past bits including the present bit, and wherein said transceiver circuit includes 2ⁿ receivers corresponding to 2ⁿ kinds of compensation voltages and a selection circuit for selecting a receiver output corresponding to an actual bit sequence.

74. The transceiver circuit as claimed in claim 61, further comprising:

an equalization circuit, provided for said driver or said receiver or for both said driver and said receiver, for compensating for a characteristic of said signal transmission line, and wherein said compensation voltage generating circuit includes a unit for receiving a test pattern and adjusting so as to minimize an interference value from the driver at the same end and intersymbol interference introduced into a signal transmitted from the driver at the opposite end.

75. The transceiver circuit as claimed in claim 61, further comprising:

an impedance holding circuit for holding an output impedance of said driver at a constant value.

76. The transceiver circuit as claimed in claim 61, wherein transient time of the transmit signal output from said driver is set substantially equal to bit time T.

77. A signal transmission system comprising a first transceiver circuit, a second transceiver circuit, and a signal transmission line connecting between said first and second transceiver circuits, wherein at least one of said first and second transceiver circuits is a transceiver circuit comprising:

a driver for outputting a transmit signal onto a signal transmission line;

a receiver for receiving a receive signal from said signal transmission line; and

a compensation voltage generating circuit for generating a compensation voltage used to compensate for an interference voltage caused by said driver, and for supplying said compensation voltage to said receiver, wherein bidirectional signal transmission is performed by controlling an output level of said compensation voltage generating circuit in accordance with the phase relationship between said transmit signal and said receive signal.

78. The signal transmission system as claimed in claim 77, wherein said driver is a constant-current driver.

79. The signal transmission system as claimed in claim 78, wherein said driver includes:

a first driver unit array having a plurality constant-current driver units; and

a second driver unit array having a plurality constant-current driver units, transmit signals being sequentially output by switching between said first and second driver unit arrays.

80. The signal transmission system as claimed in claim 79, wherein each of said driver unit arrays controls the operating condition of said plurality of constant-current driver units in said each driver unit array and thereby adjusts a transient characteristic of said transmit signal.

81. The signal transmission system as claimed in claim 80, wherein said transceiver circuit further comprises:

a predriver for driving each of said driver unit arrays, wherein said predriver is driven by a 4n-phase clock whose cycle is twice as long as bit time T, where n denotes the number of driver units in said each driver unit array.

82. The signal transmission system as claimed in claim 77, wherein said compensation voltage generating circuit is a replica driver having the same circuit configuration as that of said driver and driven by the same data as that for said driver, and includes a unit for controlling the output amplitude and transient time of said replica driver.

83. The signal transmission system as claimed in claim 82, wherein said driver comprises a plurality of driver units, and said replica driver is similar in configuration to one of said driver units constituting said driver.

84. The signal transmission system as claimed in claim 83, wherein said compensation voltage generating circuit further includes:

a correction circuit for generating, based on a past output bit, a correction signal for improving the accuracy of said compensation voltage at decision timing in said receiver.

85. The signal transmission system as claimed in claim 77, wherein said compensation voltage generating circuit generates said compensation voltage based on a data sequence consisting of the present bit and past bit of said transmit signal output from said driver and in accordance with the phase relationship between said transmit signal and said receive signal.

86. The signal transmission system as claimed in claim 85, wherein said transceiver circuit further comprises:

a unit for determining prior to actual signal transmission a compensation voltage for a boundary across which a decision in said receiver changes from data “

0”

to data “

1”

or from data “

1”

to data “

0”

, by transmitting a test pattern from the driver at one end while setting an output current level at zero in the driver at the other end; and

a unit for storing said determined compensation voltage, and wherein actual signal transmission is performed using said stored compensation voltage.

87. The signal transmission system as claimed in claim 77, wherein said compensation voltage generating circuit includes:

a plurality of compensation voltage correction circuits each for generating a voltage level that depends on a data sequence consisting of the present bit and past bit of said transmit signal output from said driver and on the phase difference between said transmit signal and said receive signal; and

a selection circuit for selecting the output of one of said plurality of compensation voltage correction circuits in accordance with said data sequence.

88. The signal transmission system as claimed in claim 87, wherein said transceiver circuit further comprises:

a unit for determining prior to actual signal transmission a compensation voltage for a boundary across which a decision in said receiver changes from data “

0”

to data “

1”

or from data “

1”

to data “

0”

, by transmitting a test pattern from the driver at one end while setting an output current level at zero in the driver at the other end; and

a unit for storing said determined compensation voltage, and wherein actual signal transmission is performed using said stored compensation voltage.

89. The signal transmission system as claimed in claim 77, wherein a compensation offset value is determined based on the value of a bit sequence of n past bits including the present bit, and wherein said transceiver circuit includes 2ⁿ receivers corresponding to 2ⁿ kinds of compensation voltages and a selection circuit for selecting a receiver output corresponding to an actual bit sequence.

90. The signal transmission system as claimed in claim 77, wherein said transceiver circuit further comprises:

an equalization circuit, provided for said driver or said receiver or for both said driver and said receiver, for compensating for a characteristic of said signal transmission line, and wherein said compensation voltage generating circuit includes a unit for receiving a test pattern and making an adjustment so as to minimize an interference value from the driver at the same end and intersymbol interference introduced into a signal transmitted from the driver at the opposite end.

91. The signal transmission system as claimed in claim 77, wherein said transceiver circuit further comprises:

an impedance holding circuit for holding an output impedance of said driver at a constant value.

92. The signal transmission system as claimed in claim 77, wherein transient time of the transmit signal output from said driver is set substantially equal to bit time T.

93. A signal transmission method, having a driver for outputting a transmit signal onto a signal transmission line and a receiver for receiving a receive signal from said signal transmission line, in which a compensation voltage used to compensate for an interference voltage caused by said driver is generated and supplied to said receiver, wherein bidirectional signal transmission is performed by controlling the level of said compensation voltage in accordance with the phase relationship between said transmit signal and said receive signal.

94. The signal transmission method as claimed in claim 93, wherein said compensation voltage is generated based on a data sequence consisting of the present bit and past bit of said transmit signal output from said driver and in accordance with the phase relationship between said transmit signal and said receive signal.

95. The signal transmission method as claimed in claim 94, wherein a compensation voltage for a boundary across which a decision in said receiver changes from data “

0”

to data “

1”

or from data “

1”

to data “

0”

is determined prior to actual signal transmission by transmitting a test pattern from the driver at one end while setting an output current level at zero in the driver at the other end, said determined compensation voltage is stored in memory, and actual signal transmission is performed using said stored compensation voltage.

96. The transmission method as claimed in claim 93, wherein transient time of the transmit signal output from said driver is set substantially equal to bit time T.