Embedded DRAM cache memory and method having reduced latency

• US 20050033921A1
• Filed: 09/01/2004
• Published: 02/10/2005
• Est. Priority Date: 10/04/2001
• Status: Active Grant

• Current Assignee: Joseph Jeddeloh
• Original Assignee: Joseph Jeddeloh
• Inventors: Jeddeloh, Joseph
• Granted Patent: US 7,188,217 B2
• Time in Patent Office: Days
• US Class Current: 711/118
• CPC Class Codes: G06F 12/0893 Caches characterised by their organisation or structure
• CPC Class Codes: G06F 12/0897 with two or more cache hierarchy levels with multilevel cache hierarchies G06F12/0811

Abstract

A computer system includes a processor, a system memory, and an integrated circuit system controller coupled to the processor and the system memory. The system controller includes a system memory controller coupled to the system memory, a processor interface coupled to the processor and an embedded cache memory integrated with the memory controller and the processor interface. The cache memory includes at least one DRAM array, at least one tag memory, and at least one cache memory controller. The cache memory controller initiates an access to either or both the DRAM array and the tag memory, as well as the system memory, before the cache memory controller has determined if the access will result in a cache hit or a cache miss. If the cache memory controller determines that the access will result in a cache hit, data are coupled from the DRAM array to the processor. If the cache memory controller determines that the access will result in a cache miss, data are coupled from the system memory to the processor.

Claims

1-54. -54. (Canceled)

55. A memory system for use with a processor based system having a processor and a system memory, the memory system comprising:

a system memory controller structured to control the system memory of the processor based system;

a processor interface coupled to the system memory controller, the processor interface structured to transmit information between the processor and the system memory; and

a cache memory coupled to the system memory controller and the processor interface, the cache memory being operable to receive a request for access to the cache memory, and, in response thereto, to initiate a read operation in the cache memory before determining whether the access to the cache memory will result in a cache hit, the cache memory being operable to couple read data from the cache memory to the processor in response to determining that the access will result in a cache hit.

56. The memory system of claim 55 wherein the cache memory is further operable to apply to the system memory controller a request for access to the system memory responsive to receiving the request for access to the cache memory and before the cache memory has determined whether the access to the cache memory will result in a cache hit, the cache memory being further operable to couple data accessed from the system memory to the processor responsive to the cache memory determining that the access to the cache memory will not result in a cache hit.

57. The memory system of claim 55 wherein the cache memory is further operable in response to determining that the access will not result in a cache hit to apply a request to the system memory controller for access to the system memory.

58. The memory system of claim 57 wherein the cache memory is further operable to receive data from the system memory responsive to the request for access to the system memory and to write the data received from the system memory to the cache memory.

59. The memory system of claim 55 wherein the system memory controller, processor interface and cache memory are fabricated as an integrated circuit on a common substrate.

60. A memory system for use with a processor based system having a processor and a system memory, the memory system comprising:

a system memory controller structured to control the system memory of the processor based system;

a processor interface coupled to the system memory controller, the processor interface structured to transmit information between the processor and the system memory; and

a cache memory coupled to the system memory controller and the processor interface, the cache memory being operable to receive a request for access to the cache memory, and, in response thereto to initiate an access to the cache memory and an access to the system memory, the cache memory being operable to initiate an access to the system memory before the cache memory has determined whether the access to the cache memory will result in a cache hit, the cache memory being further operable to couple data accessed from the system memory to the processor responsive to the cache memory determining that the access to the cache memory will not result in a cache hit.

61. The memory system of claim 60 wherein the cache memory is operable to initiate a read operation in the cache memory before the cache memory has determined whether the access to the cache memory will result in a cache hit.

62. The memory system of claim 61 wherein the cache memory is further operable to couple read data from the cache memory to the processor in response to determining that the access will result in a cache hit.

63. The memory system of claim 60 wherein, in response to determining that the access will not result in a cache hit, the cache memory is operable to receive data from the system memory responsive to the request for access to the system memory and to write the data received from the system memory to the cache memory.

64. The memory system of claim 60 wherein the system memory controller, processor interface and cache memory are fabricated as an integrated circuit on a common substrate.

65. A computer system comprising:

a processor;

a system memory;

a system controller coupled to the processor and to the system memory, the system controller comprising;

a memory controller coupled to the system memory, the memory controller being structured to control the system memory;

a processor interface coupled to the processor, the processor interface structured to transmit information between the processor and the memory controller; and

a cache memory coupled to the memory controller, the cache memory being operable to receive a request for access to the cache memory, and, in response thereto, to initiate a read operation in the cache memory before determining whether the access to the cache memory will result in a cache hit, the cache memory being operable to couple read data from the cache memory to the processor in response to determining that the access will result in a cache hit.

66. The computer system of claim 65 wherein the cache memory is further operable to apply to the memory controller a request for access to the system memory responsive to receiving the request for access to the cache memory and before the cache memory has determined whether the access to the cache memory will result in a cache hit, the cache memory being further operable to couple data accessed from the system memory to the processor responsive to the cache memory determining that the access to the cache memory will not result in a cache hit.

67. The computer system of claim 65 wherein the cache memory is further operable in response to determining that the access will not result in a cache hit to apply a request to the memory controller for access to the system memory.

68. The computer system of claim 67 wherein the cache memory is further operable to receive data from the system memory responsive to the request for access to the system memory and to write the data received from the system memory to the cache memory.

69. The computer system of claim 65 wherein the memory controller, processor interface and cache memory are fabricated as an integrated circuit on a common substrate.

72. The computer system of claim 68 wherein the cache memory is further operable to couple read data from the cache memory to the processor in response to determining that the access will result in a cache hit.

70. A computer system comprising:

a processor;

a system memory;

a system controller coupled to the processor and to the system memory, the system controller comprising;

a memory controller coupled to the system memory, the system memory controller being structured to control the system memory;

a processor interface coupled to the processor, the processor interface structured to transmit information between the processor and the system controller; and

a cache memory coupled to the memory controller and the processor interface, the cache memory being operable to receive a request for access to the cache memory, and, in response thereto to initiate an access to the cache memory and an access to the system memory, the cache memory being operable to initiate an access to the system memory before the cache memory has determined whether the access to the cache memory will result in a cache hit, the cache memory being further operable to couple data accessed from the system memory to the processor responsive to the cache memory determining that the access to the cache memory will not result in a cache hit.

71. The computer system of claim 70 wherein the cache memory is operable to initiate a read operation in the cache memory before the cache memory has determined whether the access to the cache memory will result in a cache hit.

73. The computer system of claim 70 wherein, in response to determining that the access will not result in a cache hit, the cache memory is operable to receive data from the system memory responsive to the request for access to the system memory and to write the data received from the system memory to the cache memory.

74. The computer system of claim 70 wherein the system controller comprises an integrated circuit in which the memory controller, processor interface and cache memory are fabricated in a common integrated circuit.

75. In a processor-based system having a memory requester, a system memory, and a cache memory, a method of accessing data or instructions stored in the system memory and possibly also in the cache memory, the method comprising:

generating at the memory requester a request for access to the data or instructions;

coupling the request for access to the data or instructions to the cache memory;

receiving at the cache memory the request for access to the data or instructions; and

initiating an access to the system memory for the data or instructions before determining whether the access to the cache memory will result in a cache hit or a cache miss.

76. The method of claim 75, further comprising coupling data or instructions from the cache memory to the memory requester in response to determining that the access to the cache memory will result in a cache hit.

77. The method of claim 75, further comprising coupling data or instructions from the system memory to the memory requestor in response to determining that the access to the cache memory will result in a cache miss.

78. The method of claim 77, further comprising writing the data or instructions received from the system memory to the cache memory.

79. The method of claim 75, further comprising applying to the system memory a request for access to the system memory responsive to receiving the request for access to the data or instructions.

80. The method of claim 79 wherein the act of applying a request for access to the system memory to the system memory comprises applying the request for access to the system memory to the system memory before determining whether the access to the cache memory will result in a cache hit or a cache miss.

81. In a computer system having a memory requester, a system memory, and a cache memory, a method of accessing data or instructions stored in the system memory and possibly also in the cache memory, the method comprising:

generating at the memory requester a request for access to the data or instructions;

coupling the request for access to the data or instructions to the cache memory;

receiving at the cache memory the request for access to the data or instructions;

initiating an access to the cache memory responsive to receiving the request for access to the data or instructions; and

applying to the system memory a request for access to the system memory responsive to receiving the request for access to the data or instructions, the request for access to the system memory being applied to the system memory before determining whether the access to the cache memory will result in a cache hit or a cache miss.

82. The method of claim 81, further comprising coupling data or instructions from the cache memory to the memory requestor in response to determining that the access to the cache memory will result in a cache hit.

83. The method of claim 81, further comprising coupling data or instructions from the system memory to the memory requestor in response to determining that the access to the cache memory will result in a cache miss.

84. The method of claim 83, further comprising writing the data or instructions received from the system memory to the cache memory.

85. The method of claim 81 wherein the act of initiating an access to the cache memory responsive to receiving the request for access to the data or instructions comprises initiating the access to the cache before determining whether the access to the cache memory will result in a cache hit or a cache miss.

86. In a computer system having a memory requester, a system memory, and a cache memory, a method of accessing data or instructions stored in the system memory and possibly also in the cache memory, the method comprising:

generating at the memory requester a request for access to the data or instructions;

coupling the request for access to the data or instructions to the cache memory;

receiving at the cache memory the request for access to the data or instructions; and

initiating a read operation in the cache memory responsive to receiving the request for access to the data or instructions, the read operation being initiated before determining whether the access to the cache memory will result in a cache hit or a cache miss.

87. The method of claim 86, further comprising coupling data or instructions from the cache memory to the memory requestor in response to determining that the access to the cache memory will result in a cache hit.

88. The method of claim 86, further comprising coupling data or instructions from the system memory to the memory requestor in response to determining that the access to the cache memory will result in a cache miss.

89. The method of claim 88, further comprising writing the data or instructions received from the system memory to the cache memory.

90. The method of claim 86, further comprising applying to the system memory a request for access to the system memory responsive to receiving the request for access to the data or instructions, the request for access to the system memory being applied to the system memory before determining whether the access to the cache memory will result in a cache hit or a cache miss.