Common feature mode for microprocessors in a multiple microprocessor system

• US 20050033950A1
• Filed: 09/13/2004
• Published: 02/10/2005
• Est. Priority Date: 04/11/2000
• Status: Active Grant

• Current Assignee: Microsoft Technology Licensing LLC (Microsoft Corporation)
• Original Assignee: Microsoft Corporation
• Inventors: Williams, David W., See, Valerie R.
• Granted Patent: US 7,249,247 B2
• Time in Patent Office: Days
• US Class Current: 713/1
• CPC Class Codes: G06F 8/61 Installation
• CPC Class Codes: G06F 8/64 Retargetable
• CPC Class Codes: G06F 9/30003 Arrangements for executing specific machine instructions
• CPC Class Codes: G06F 9/4405 Initialisation of multiprocessor systems

Abstract

A mechanism whereby a set of microprocessors may be set to a common mode in which the microprocessors utilize one or more features that are common to all microprocessors. The common mode facilitates proper multiprocessor operation and permits a fix (e.g., a microcode patch) to be applied to each of the microprocessors based on this common mode. More particularly, at system startup, firmware or software can detect whether microprocessors are set to run in different modes (e.g., steppings) in a multiprocessor system. If not, the microprocessors are allowed to run in their normal mode, such as by writing a particular value (e.g., zero) to a configuration register associated with each microprocessor. If features are mixed, a different value can be written, (e.g., one), which tells each microprocessor to revert to a common mode of operation for that family of microprocessors, such as corresponding to a common stepping and/or clock speed. A common set of microcode patches may be downloaded to the microprocessors. Alternatively, the various microprocessors may also be instructed to run in a particular mode that emulates a particular stepping, e.g., by writing into the configuration register or registers a number between one and M that corresponds to a common stepping among the microprocessors.

Claims

1. In a computing environment, a method comprising:

detecting a first computing element having a plurality of operating modes;

detecting a second computing element; and

changing a mode on the first computing element to correspond to an operating mode of the second computing element.

2. The method of claim 1 further comprising, changing a mode on at least one other computing element to correspond to the operating mode of the second computing element.

3. The method of claim 1 wherein changing the mode on the first computing element comprises changing the first computing element to operate with another stepping.

4. The method of claim 1 wherein changing the mode on the first computing element comprises changing the first computing element to operate with another instruction set.

5. The method of claim 4 wherein changing the mode on the first computing element comprises changing the first computing element to operate with another stepping.

6. The method of claim 1 wherein the first computing element comprises a central processing unit and the second computing element comprises a graphics processing unit.

7. The method of claim 1 wherein the first computing element comprises a digital signal processing unit.

8. The method of claim 1 wherein the first computing element comprises a programmable gate array.

9. The method of claim 1 further comprising changing a mode on the second computing element.

10. The method of claim 1 wherein changing the mode on the first computing element comprises communicating a message to the first computing element over a network.

11. The method of claim 1 wherein changing the mode on the first computing element comprises changing a processor that primarily handles input/output operations to a processor that primarily handles computational operations.

12. At least one computer-readable medium having computer-executable instructions which when executed perform the method of claim 1.

32. At least one computer-readable medium having computer-executable instructions which when executed perform the method of claim 1.

13. In a computing environment, a system comprising:

a plurality of computing elements; and

an intermediary mechanism coupled to a first computing element to cause a change to an operating mode of the first computing element to correspond to an operating mode of a second computing element.

14. The system of claim 13, wherein the intermediary mechanism writes information to at least one register.

15. The computer system of claim 13, wherein the intermediary mechanism is coupled to the first computing element over a network connection.

16. The system of claim 13, further comprising firmware operatively associated with at least one of the computing elements, and wherein the intermediary mechanism is incorporated into the firmware.

17. The system of claim 13, wherein the intermediary mechanism comprises a web service.

18. The system of claim 13 further comprising at least one other computing element having a changeable mode caused to be changed by the intermediary mechanism to correspond to the operating mode of the second computing element.

19. The system of claim 13 wherein the intermediary mechanism causes the first computing element to operate with another stepping.

20. The system of claim 13 wherein the intermediary mechanism causes the first computing element to operate with another instruction set.

21. The system of claim 20 wherein the intermediary mechanism causes the first computing element to operate with another stepping.

22. The system of claim 13 wherein the first computing element comprises a central processing unit and the second computing element comprises a graphics processing unit.

23. The system of claim 13 wherein the first computing element comprises a digital signal processing unit.

24. The system of claim 13 wherein the first computing element comprises a programmable gate array.

25. The system of claim 13 wherein the intermediary mechanism causes a mode change to the second computing element.

26. The system of claim 13 wherein the intermediary mechanism, the first computing element and the second computing element are networked.

27. The system of claim 13 wherein the first computing element is changed from a mode that primarily handles input/output operations to a mode that primarily handles computational operations.

28. In a computing environment, a method comprising:

providing a first computing element having a plurality of operating modes;

providing a second computing element having at least one operating mode; and

synchronizing the modes to enhance interoperability between the first and first computing elements.

29. The method of claim 28 wherein synchronizing the modes comprises changing an instruction set.

30. The method of claim 28 wherein the first computing element comprises a microprocessor, and wherein synchronizing the modes comprises causing the microprocessor to run with a different stepping.

31. The method of claim 28 wherein the first computing element communicates with the second computing element via a network.