Method and apparatus for mapping platform-based design to multiple foundry processes

• US 20050034087A1
• Filed: 01/29/2004
• Published: 02/10/2005
• Est. Priority Date: 08/04/2003
• Status: Abandoned Application

• Current Assignee: Bell Semiconductor, LLC (Hilco Inc. (d/b/a Hilco Global))
• Original Assignee: Bell Semiconductor, LLC (Hilco Inc. (d/b/a Hilco Global))
• Inventors: Boyle, Douglas B., Hamlin, Christopher L., Koford, James S.
• Application Number:
  US10/768,588
• Publication Number:
  US 20050034087A1
• Time in Patent Office: Days
• US Class Current: 716/54
• CPC Class Codes: G06F 30/00 Computer-aided design [CAD]

Abstract

The present invention is directed to a method and apparatus for mapping platform-based design to multiple foundry processes. According to an exemplary aspect of the present invention, a method for mapping platform-based design to multiple foundry processes may include the following steps. First, availability of required features of a design in a target foundry process may be checked. The target foundry process must provide all the features that are used in the design. The design may include base wafer layers and metal stack layers. Then, a base wafer/metal stack interface layer for the design may be selected. Next, compatible blocks between different base wafer processes may be created. Then, a physical design library for the design may be created. Next, a logic design and timing library for the design may be created. This way, the design may be mapped to different foundry processes.

Claims

1. A method for mapping platform-based design to multiple foundry processes, comprising steps of:

(a) checking availability of required features of a design in a target foundry process, said design including base wafer layers and metal stack layers;

(b) selecting a base wafer/metal stack interface layer for said design;

(c) creating compatible blocks between a first base wafer process of said target foundry process and a second base wafer process of a second foundry process;

(d) creating a physical design library for said design; and

(e) creating a logic design and timing library for said design,

whereby said design is implemented in both said target foundry process and said second foundry process.

2. The method of claim 1, further comprising checking at least one of topological constraints, process and reliability constraints, and performance and electrical constraints on said target foundry process.

3. The method of claim 1, wherein said base wafer/metal stack interface layer is selected at Localint or Vial layer within said metal stack layers.

4. The method of claim 1, wherein said compatible blocks include at least one of I/O cells, SRAM, sea-of-transistors, IP blocks, standard cells that may be used to develop additional IP blocks.

5. The method of claim 1, wherein said step (c) is used to optimize at least one of layout compaction, performance and yield.

6. The method of claim 1, wherein said step (c) comprising:

(c1) when said metal stack layers are same for said target foundry process and said second foundry process, naming said base wafer layers implemented by said target foundry process as a first set of base wafer layers, and said base wafer layers implemented by said second foundry process as a second set of base wafer layers; and

(c2) constructing a composite layout compacting problem for a block for said first set of base wafer layers, said second set of base wafer layers, and said metal stack layers to enable objects in said first set of base wafer layers have constraints with each other and with objects in said metal stack layers, and objects in said second set of base wafer layers have constraints with one another and with objects in said metal stack layers.

7. The method of claim 1, wherein said step (e) comprising:

(e1) characterizing blocks in said target foundry process and said second foundry process; and

(e2) applying guard bands to select a yield versus performance tradeoff at a system design level.

8. An apparatus for mapping platform-based design to multiple foundry processes, comprising:

(a) means for checking availability of required features of a design in a target foundry process, said design including base wafer layers and metal stack layers;

(b) means for selecting a base wafer/metal stack interface layer for said design;

(c) means for creating compatible blocks between a first base wafer process of said target foundry process and a second base wafer process of a second foundry process;

(d) means for creating a physical design library for said design; and

(e) means for creating a logic design and timing library for said design, wherein said design is implemented in both said target foundry process and said second foundry process.

9. The apparatus of claim 8, further comprising means for checking at least one of topological constraints, process and reliability constraints, and performance and electrical constraints on said target foundry process.

10. The apparatus of claim 8, wherein said base wafer/metal stack interface layer is selected at Localint or Vial layer within said metal stack layers.

11. The apparatus of claim 8, wherein said compatible blocks include at least one of I/O cells, SRAM, sea-of-transistors, IP blocks, standard cells that may be used to develop additional IP blocks.

12. The apparatus of claim 8, wherein said means (c) is used to optimize at least one of layout compaction, performance and yield.

13. The apparatus of claim 8, wherein said means (c) comprising:

(c1) when said metal stack layers are same for said target foundry process and said second foundry process, means for naming said base wafer layers implemented by said target foundry process as a first set of base wafer layers, and said base wafer layers implemented by said second foundry process as a second set of base wafer layers; and

(c2) means for constructing a composite layout compacting problem for a block for said first set of base wafer layers, said second set of base wafer layers, and said metal stack layers to enable objects in said first set of base wafer layers have constraints with each other and with objects in said metal stack layers, and objects in said second set of base wafer layers have constraints with one another and with objects in said metal stack layers.

14. The apparatus of claim 8, wherein said means (e) comprising:

(e1) means for characterizing blocks in said target foundry process and said second foundry process; and

(e2) means for applying guard bands to select a yield versus performance tradeoff at a system design level.

15. A computer-readable medium having computer-executable instructions for performing a method for mapping platform-based design to multiple foundry processes, said method comprising steps of:

(a) checking availability of required features of a design in a target foundry process, said design including base wafer layers and metal stack layers;

(b) selecting a base wafer/metal stack interface layer for said design;

(c) creating compatible blocks between a first base wafer process of said target foundry process and a second base wafer process of a second foundry process;

(d) creating a physical design library for said design; and

(e) creating a logic design and timing library for said design, whereby said design is implemented in both said target foundry process and said second foundry process.

16. The computer-readable medium of claim 15, wherein said method further comprising checking at least one of topological constraints, process and reliability constraints, and performance and electrical constraints on said target foundry process.

17. The computer-readable medium of claim 15, wherein said base wafer/metal stack interface layer is selected at Localint or Vial layer within said metal stack layers.

18. The computer-readable medium of claim 15, wherein said compatible blocks include at least one of I/O cells, SRAM, sea-of-transistors, IP blocks, standard cells that may be used to develop additional IP blocks.

19. The computer-readable medium of claim 15, wherein said step (c) is used to optimize at least one of layout compaction, performance and yield.

20. The computer-readable medium of claim 15, wherein said step (c) comprising:

(c1) when said metal stack layers are same for said target foundry process and said second foundry process, naming said base wafer layers implemented by said target foundry process as a first set of base wafer layers, and said base wafer layers implemented by said second foundry process as a second set of base wafer layers; and

(c2) constructing a composite layout compacting problem for a block for said first set of base wafer layers, said second set of base wafer layers, and said metal stack layers to enable objects in said first set of base wafer layers have constraints with each other and with objects in said metal stack layers, and objects in said second set of base wafer layers have constraints with one another and with objects in said metal stack layers.

21. The computer-readable medium of claim 15, wherein said step (e) comprising:

(e1) characterizing blocks in said target foundry process and said second foundry process; and

(e2) applying guard bands to select a yield versus performance tradeoff at a system design level.

22. A method for mapping platform-based design to multiple foundry processes, comprising steps of:

(a) checking availability of required features of a design in a target foundry process;

(b) substituting blocks for said target foundry process into said design;

(c) performing physical design rule check and electrical checks on said design; and

(d) generating masks for base wafer layers of said target foundry process.

23. A computer-readable medium having computer-executable instructions for performing a method for mapping platform-based design to multiple foundry processes, said method comprising steps of:

(a) checking availability of required features of a design in a target foundry process;

(b) substituting blocks for said target foundry process into said design;

(c) performing physical design rule check and electrical checks on said design; and

(d) generating masks for base wafer layers of said target foundry process.