Polycrystalline tft uniformity through microstructure mis-alignment

• US 20050034653A1
• Filed: 08/27/2002
• Published: 02/17/2005
• Est. Priority Date: 08/27/2001
• Status: Active Grant

• Current Assignee: Trustees Of Columbia University In The City Of New York (Columbia University)
• Original Assignee: Trustees Of Columbia University In The City Of New York (Columbia University)
• Inventors: Van Der Wilt, Paul Christiaan, Im, James
• Granted Patent: US 7,160,763 B2
• Time in Patent Office: Days
• US Class Current: 117/84
• CPC Class Codes: C30B 13/24 using electromagnetic waves
• CPC Class Codes: C30B 29/06 Silicon

Abstract

Methods of making a polycrystalline silicon thin-film transistor having a uniform microstructure. One exemplary method requires receiving a polycrystalline silicon thin film having a grain structure which is periodic in at least a first direction, and placing at least portions (410, 420) of one or more thin-film transistors on the received film such that they are tilted relative to the periodic structure of the thin film.

Claims

1. A method of making a polycrystalline device including two or more thin-film transistors of substantially uniform microstructure, comprising the steps of:

(a) receiving a polycrystalline silicon thin film having a grain structure which is periodic in at least a first direction; and

(b) placing at least portions of two or more thin-film transistors on said received film tilted at an angle relative to said periodic structure of said thin film, such that that the number of long grain boundaries in any of said portions remains substantially uniform.

2. The method of claim 1, wherein said receiving step comprises the step of receiving a polycrystalline silicon thin film formed by a sequential lateral solidification process.

3. The method of claim 1, wherein said portions of said two or more thin-film transistors comprise active channel regions having a width W.

4. The method of claim 3, wherein said periodic structure of said thin film is λ

, m is a variable, and said placing step comprises the step of placing said active channel regions on said received film such that said active channel regions are tilted at an angle θ

relative to said periodic structure of said thin film, where W sin(θ

)=mλ

.

5. The method of claim 4, wherein m substantially equal to an integer.

6. The method of claim 4, wherein m is equal to an integer.

7. The method of claim 4, wherein m is equal to the integer 1.

8. A method of making a device including thin-film transistors, comprising the steps of:

(a) receiving a polycrystalline silicon thin film having a grain structure which is periodic in at least a first direction in an amount λ

; and

(b) placing at least portions of one or more thin-film transistors having a width W on said received film tilted at an angle θ

relative to said periodic structure λ

of said thin film, such that W sin(θ

)=mλ

, where m is substantially equal to an integer.

9. The method of claim 8, wherein said receiving step comprises the step of receiving a polycrystalline silicon thin film formed by a sequential lateral solidification process.

10. The method of claim 8, wherein said portions of said one or more thin-film transistors comprise active channel regions having a width W.

11. The method of claim 10, wherein m is equal to an integer.

12. The method of claim 10, wherein m is equal to the integer 1.

13. A device including two or more polycrystalline silicon thin-film transistors of substantially uniform microstructure, comprising:

(a) a polycrystalline silicon thin film having a grain structure which is periodic in at least a first direction; and

(b) at least two or more thin-film transistor portions placed on said received film, each tilted at an angle relative to said periodic structure of said thin film, such that that the number of long grain boundaries in any of said portions remains substantially uniform.

14. The device of claim 13, wherein said polycrystalline silicon thin film comprises thin film formed by a sequential lateral solidification process.

15. The device of claim 13, wherein said portions of said two or more thin-film transistors comprise active channel regions having a width W.

16. The device of claim 13, wherein said periodic structure of said thin film is λ

, m is a variable, and said active channel regions are tilted at an angle θ

relative to said periodic structure of said thin film, where W sin(θ

)=mλ

.

17. The device of claim 16, wherein m is substantially equal to an integer.

18. The device of claim 16, wherein m is equal to an integer.

19. The device of claim 16, wherein m is equal to the integer 1.