Trench MOSFET with increased channel density

• US 20050035402A1
• Filed: 09/27/2004
• Published: 02/17/2005
• Est. Priority Date: 08/28/2000
• Status: Active Grant

• Current Assignee: Prasad Venkatraman
• Original Assignee: JP Morgan Chase Bank, N.A. (JP Morgan Chase & Co)
• Inventors: Venkatraman, Prasad
• Granted Patent: US 6,987,040 B2
• Time in Patent Office: Days
• US Class Current: 257/330
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 21/823487 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823431
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: Y10S 257/923 with means to optimize electrical conductor current carrying capacity, e.g. particular conductor aspect ratio

Abstract

A MOSFET device (50) has a trench (60) extending from a major surface (56) of the device (50). Within the trench (60), a gate structure (62) is formed where the top surface (64) is below the major surface(56). Source regions (66, 68) are formed along a vertical wall (84) inside of the trench (60). The source regions (66, 68) have a horizontal component along the major surface (56) and a vertical component extending the vertical wall (84). The majority of the source regions (66, 68) are formed along the vertical wall (84) within the trench (60). A typical aspect ratio of the vertical length of the source regions (66, 68) to the horizontal width is greater than 3:1. An Inter-layer dielectric (ILD) layer (74) is formed on the gate structure (62) within the trench (60) below the major surface (56). A metal electrode layer (82) is formed above the major surface (56) where a portion is formed inside the trench (60) making source contact to the source regions (66, 68) inside the trench (60) along the vertical wall (84) of the trench (60).

Claims

1-21. -21. Cancelled

22. A method for forming a semiconductor device having a major surface, comprising:

providing a semiconductor material body having a trench with a vertical side, wherein the trench extends from the major surface to a depth within the semiconductor material body;

forming a gate structure having a top surface within the trench, wherein the top surface of the gate structure is below the major surface;

forming a source region along the vertical side of the trench, wherein the vertical side of the source region inside the trench is greater than a horizontal width of the source region along the major surface of the semiconductor material body; and

forming a conductive electrode layer on the major surface making contact with the source region along its vertical side.

23. The method of claim 22, wherein the step of forming the source region forming the source region using angled ion implantation.

24. The method of claim 22, wherein the step of forming the source region includes forming the source region by diffusing from a predeposited glass layer.

25. The method of claim 22, wherein the step of providing the semiconductor material body includes providing a semiconductor material body having a striped trench with a vertical sidewall, and wherein the step of forming the source region includes forming the source region along a portion of the vertical sidewall, and wherein the method further comprises the step of:

forming a doped region along a horizontal surface of the semiconductor material and along another portion of the sidewall, wherein the conductive electrode layer makes electrical contact to the doped region along the vertical sidewall.

26. A method of making a semiconductor device comprising the steps of:

providing a semiconductor material body having a trench extending from a major surface to a depth within the semiconductor material body;

forming a source region vertically along a sidewall of the trench above the gate structure and below the major surface of the semiconductor material body;

forming a gate structure within the trench; and

forming an interlayer dielectric (ILD) region within the trench above the gate structure and below the major surface of the semiconductor material body.

27. The method of claim 26 wherein the step of providing the semiconductor material body includes providing a substrate region of the first conductivity type disposed in the semiconductor material body and having a base region of the second conductivity type extending from the major surface of the semiconductor material body.

28. The method of claim 27 wherein the step of providing the semiconductor material body includes providing a semiconductor material body having an epi region of the first conductivity type between the substrate region and the base region, wherein the epi region has a lower dopant concentration than the substrate region.

29. The method of claim 27, wherein the step of providing the semiconductor material body includes providing a semiconductor material body having a doped region of the second conductivity type within the base region, wherein the doped region has a higher dopant concentration than the the base region.

30. The method of claim 26, further including the step of forming a conductive electrode layer, wherein a portion of the conductive electrode layer extends within the trench and onto the ILD region making electrical contact to the source region inside the trench.

31. A process for forming a semiconductor device having a major surface comprising the steps of:

providing a first region of semiconductor material having a first conductivity type and a second region of a second conductivity type disposed above the first region;

forming a trench extending vertically from the major surface through the second region;

forming a third region of the first conductivity type in the second region having a vertical component along the trench, wherein the vertical component of the third region along the trench is greater than a horizontal component of the third region; and

forming a conductive electrode layer formed below the major surface making contact to the third region inside the trench along the vertical component of the third region of the semiconductor device.

32. The method of claim 31, further including the step of forming a fourth region of the first conductivity type between the first region and the second region such that the trench extends partially into the fourth region.

33. The method of claim 31, further including the step of forming a gate structure within the trench, wherein the gate structure has a top surface below the major surface of the semiconductor device.

34. The method of claim 33, wherein the step of forming the gate structure comprises the steps of:

forming a gate dielectric layer within the trench;

filling the trench with polycrystalline semiconductor material; and

removing a portion of the polycrystalline semiconductor material to provide the top surface below the major surface of the semiconductor device.

35. The method of claim 33, further including the step of forming an ILD region in the trench above the top surface of the gate structure.

36. The method of claim 35, wherein the step of forming the ILD region includes forming an ILD region so that a portion of the conductive electrode layer extends within the trench onto the ILD region.

37. The method of claim 31, further including the step of forming a doped region within the second region, and having the second conductivity type, wherein the doped region has a higher dopant concentration than the second region.

38. The method of claim 31, wherein the step of forming the trench comprises the steps of:

forming a first dielectric layer over the major surface;

forming a second dielectric layer over the first dielectric layer;

forming an opening in the first and second dielectric layers;

forming spacers in the opening;

etching the trench through the opening;

forming a sacrificial dielectric layer on sidewalls of the trench; and

removing the sacrificial dielectric layer and the spacers.

39. The method of claim 38, wherein the step of forming the first dielectric layer includes forming an oxide layer, and wherein the step of forming the second dielectric layer includes forming a nitride layer.

40. The method of claim 38, wherein the step of forming the sacrificial dielectric layer includes forming a sacrificial oxide layer, wherein the formation of the sacrificial oxide layer causes a sidewall to pull back under a spacer to substantially align the sidewall to an edge of the second dielectric layer.

41. The method of claim 31, wherein the step of forming the third region includes forming a third region having a ratio of vertical length to horizontal width greater than 3:

1.